Vitesse Semiconductor Corporation

Other

Network Systems Corporation

John P Mullaney

Gary Brian Lee

Denton G Wicklund

An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

High speed cross point switch routing circuit with word-synchronous serial back plane

A seamless clock distribution scheme for a system incorporating sequential digital logic devices disposed on multiple parallel boards for reducing or substantially eliminating skew. The multiple parallel boards are positioned on and project outward from one side of a centerplane. A single clock board, generating multiple copies of the system clock and mounted at a right angle to the parallel boards on the opposite side of the centerplane are connected by shared pins passing through apertures formed in the centerplane. This shared pin connection allows for simple, though near-ideal transmission of the clock signal copies between the parallel logic boards and the clock board with a minimum mismatch of the clock signal between two parallel boards.

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Minneapolis, MN, United States of America

John P Mullaney