Motorola Corporation

John P Monson

Donald G Newberg

David G Wiatrowski

Christopher N Kurby

Robert D Logalbo

Krsman Martinovich

Donald R Beyer

Paul A Kuban

An uncorrectable set of input vectors (303), comprising a primary input vector (P) and a secondary set of input vectors (S), is provided at a sender (301). The secondary set of input vectors is error correction encoded and modulated with a predetermined input vector (PIV) to produce a secondary set of modulated vectors (S'). A predetermined codeword (PC) is sent along with the secondary set of modulated vectors to a target (302). At the target, the predetermined codeword is decoded and the resulting decoded predetermined codeword 306 is used to demodulate the secondary set of modulated vectors. As the predetermined codeword is chosen such that, when decoded, it is not identical to the predetermined input vector, the secondary set of demodulated vectors (S') will contain a sufficient number of errors to indicate to the target that the set of input vectors is uncorrectable.

Method and apparatus for indicating uncorrectable errors to a target

A method of synchronizing a plurality of remote site transmitters (200) in a digital simulcast transmission system is described that enables use of four-level modulation on two-level modulation systems. A synchronization signal is transmitted at a predetermined data rate from a prime site, which signal might include a synchronization pattern having a first and a second portion. The first portion of the synchronization pattern is used for synchronization, while the second portion indicates the completion of the first portion. The method includes detecting (205, 320) of the first portion of the synchronization pattern. Each remote site transmitter (200) further has a modulation clock having a phase polarity which is selected (215, 324) in response to the detection of the first portion of the synchronization signal.

Synchronization method and apparatus for simulcast transmission system

An improved clock recovery enchancement circuit is provided that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of the bit rate clock, that is 180.degree. out of phase with the recovering clock, thereby causing the data edges to appear to be locked. The clock recovery enhancement circuit, according to the invention, provides a window signal near a predefined edge of the recovering clock which creates a disable signal such that clock adjustments may be biased towards one direction.

Clock recovery enhancement circuit

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Palatine, IL, United States of America

John P Monson