Hewlett-packard Company

John P Miller

Erik E Erlandson

Richard Ortiz

Chenmin Zhang

Michael S Vacanti

Apparatus selects a state machine bit group from a plurality of state machine bit groups of a digital system for debugging the state machine connected to the selected bit group. The apparatus is adapted to output the bits of the selected bit group using existing output pins of the digital system, and includes a first multiplexer which is adapted to be connected to the plurality of state machine bit groups for outputting the selected state machine bit group. A second multiplexer is adapted to be connected to system signals and the selected state machine bit group from the first multiplexer, and outputs one of the system signals and the selected state machine bit group via the output pins of the system. A control circuit supplies a first select signal to the first multiplexer for selecting the selected state machine bit group output by the first multiplexer, and supplies a second select signal to the second multiplexer for selecting one of the selected bit group and the system signals.

State machine bit group selection apparatus for debugging a digital system

Apparatus is disclosed for producing an output clock signal that is selectively synchronized to one of two generally free-running input clock signals that may be of the same or different frequency and phase. The apparatus is adapted to switch between the two input clock signals in a manner whereby the output clock signal does not have any clock pulses that are shrunk or narrowed.

Glitchless clock switch circuit

A network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment. By time stamping packets as they arrive, stale packets can be identified and discarded. A stale packet is a packet that has been pending in the network device longer than an active timeout interval, which may be varied based on network traffic levels to conserve network bandwidth. Packets may also be discarded to conserve packet buffer memory in the network device. For example, when an incoming packet arrives and an output buffer in which the packet must be stored is full, the output buffer is scanned to identify and discard packets that have exceeded a minimum timeout interval, thereby allowing the incoming packet to be stored in the output buffer. Many network protocols initiate the retransmission of packets after a timeout interval has expired and an acknowledge packet has not been received. The present invention conserves network bandwidth by not transmitting stale packets that either will be ignored or redundant when network traffic becomes heavy. The present invention also conserves buffer memory by allowing broadcast and multicast packets to be stored in and transmitted from a single broadcast packet output buffer. The proper packet transmission order at each port is maintained by comparing the time stamp assigned to the broadcast packet when it arrived at the network device with the time stamps of the other packets in the output buffer. Finally, the present invention provides many opportunities for collecting statistics, such as the average latency, mean latency and standard deviation of the latency of packets processed by network device.

Method and apparatus for processing network packets using time stamps

A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.

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Rocklin, CA, United States of America

John P Miller