Intel Corporation

Other

John P Lee

Aniruddha P Joshi

Geetani R Edirisooriya

Chee Hak Teh

Lance E Hacking

Ramana V Rachakonda

Mahesh K Reddy

Atul Kwatra

Lori R Borger

Pawitter P Bhatia

Daniel Nemiroff

Robert W Strong

Rajeev K Nalawadi

Amber D Huffman

Peter Munguia

Thomas M Slaight

Jeffrey L Rabe

Jasper Balraj

In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Interface logic for a multi-core system-on-a-chip (SoC)

A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.

Method, system, and apparatus to decrease CPU temperature through I/O bus throttling

A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.

Index/data register pair for indirect register access

In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.

Apparatus and method for maintaining data integrity following parity error detection

Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.

Method and apparatus for managing buffers in PCI bridges

Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Method and apparatus for an I/O controller to alert an external system management controller

Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.

Method and apparatus to permit external access to internal configuration registers

A gas-powered paint ball gun in which a magazine is attached tangentially to a firing chamber or barrel. An opening is provided in the magazine so as to release back-pressure. Paint balls are fed into the firing chamber through the magazine in a direction tangent to the firing chamber and in a direction perpendicular to the radial direction of the firing chamber or barrel. The paint balls being loaded into the firing chamber each have a limited radial distance to travel and therefore have a limited travel period. The unique configuration enables each paint ball being loaded into the chamber to come to rest in the firing chamber more rapidly and thereby reduces the risk of the gun becoming jammed. Further, this configuration enables the gun to be fired more rapidly and with greater assurance that the gun will not jam.

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Tempe, AZ, United States of America

John P Lee