Adaptec, Inc.

Stmicroelectronics Gmbh

Stmicroelectronics N.v.

Other

John P Hill

David L Dyer

Nicolas C Assouad

Nicolas C Assoud

An integrated data jitter generator for the testing of high speed serial interfaces is provided. A transmit timing generator for use in a transmit data path includes a high frequency clock generator such as a phase-locked loop or a delay-locked loop having an input for receiving an oscillator or reference clock input. A clock modulator receives both an existing low frequency modulation signal and a high frequency modulation signal. A high-speed modulated clock signal is generated to enable jitter testing by a downstream-coupled receiver. Fixed frequencies such as 3, 6, 125, 150, 250, 300, 750, or 1500 MHz are used for the high-speed modulation signal, but any high-speed modulation frequency can be used to generate the desired amount of jitter. Likewise, the amplitude of the high frequency modulation signal can also be varied as desired.

Integrated data jitter generator for the testing of high-speed serial interfaces

The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others. The present invention also includes a method of generating a timing reference signal in a IC that includes generating a high-frequency signal with the high-speed timing reference generator of a high-speed serial interface, then using a initial divider to generate a mid-frequency timing reference signal from the high-frequency timing reference signal, and then using a final divider to generate a final timing reference signal from the mid-frequency timing reference signal. In the present method, timing reference signals generated from a phase locked loop (PLL) macrocell are not required.

Clock generator for an integrated circuit with a high-speed serial interface

A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A V compensator determines a compensated command to compensate for the back electromotive force voltage produced by the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Back electromotive force voltage compensation method for switched, voltage-mode driver circuit

A VCM power driver having an input for receiving an external supply voltage VDD. A voltage-mode driver is coupled to the power supply voltage and generates a drive signal to a load. A system processor generates commands indicating a programmed voltage output desired from the voltage-mode driver. A comparator compares VDD to a reference voltage to generate an error signal. A combination mechanism generates a modified command using the error signal. The modified commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the modified command.

Supply variance compensation method for switched voltage mode voice coil motor driver circuit

A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A lead compensator determines a compensated command to compensate for an admittance function of the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Electrical time constant compensation method for switched, voltage-mode driver circuit

An electrostatic field sensor configuration and supporting signal processing electronics provides a wider bandwidth than prior art sensors, thus enabling the present sensor to replace three prior art instruments in the application of measuring atmospheric electricity. The quadrature, differential characteristics of the present sensor also provide suppression of unwanted disturbances and more accurate electrostatic field measurements. Besides application in the geophysical instrument known as a field mill, the present sensor may be employed in any system for measuring quasi-static and rapidly changing electrostatic fields.

Quadrature differential charge commutation sensor enabling wide bandwith field mills and other electrostatic field measuring devices

The invention provides a high-speed interface that transfers servo position data from the read channel integrated circuit to the drive control integrated circuit or another integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data which speeds up the data transfer. Examples of servo position data include high-resolution servo position data and coarse-resolution servo position data. A read channel integrated circuit transfers the user data and the high-resolution servo position data to a data bus, such as an NRZ bus. The data bus transfers the user data and the high-resolution servo position data to another integrated circuit, such as a drive control integrated circuit. The other integrated circuit receives the user data and the high-resolution servo position data from the data bus. The coarse-resolution servo position data can also be transferred over the data bus.

High-speed servo data interface system

The invention provides a high-speed interface that transfers user data and other data over a single unified interface between a read channel integrated circuit and another integrated circuit, such as the drive control integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data and other data which speeds up the data transfer. Examples of the other data include read channel settings, read channel performance data, and servo data. A read channel integrated circuit exchanges the user data with a data bus when the disk drive system is reading or writing the user data. The read channel integrated circuit exchanges the other data with the data bus when the disk drive system is reading servo data. The other integrated circuit exchanges the user data with the data bus when the disk drive system is reading or writing the user data. The other integrated circuit exchanges the other data with the data bus when the disk drive system is reading the servo data. The data bus transfers the user data and the other data between the integrated circuits.

High-speed unified data interface for a read channel in a disk drive system

High speed servo data interface system for transferring high resolution

Disclosed is a tracking control integrated circuit (IC) system implementation and method for controlling the gain of a digital-to-analog converter in a disk drive system. The tracking control IC system includes components defined in integrated circuit chips and components defined on a printed circuit board. The tracking control IC system is configured to be implemented in a disk drive system that includes a disk media. The tracking control IC system includes a servo controller chip that includes a compensator/processor, the digital-to-analog converter, and a switch. The switch is configured to receive a high gain signal (being Low or High) for setting the switch in an open state or a closed state. The tracking control IC system further includes a power amplifier chip having amplifying elements. The power amplifier chip has a first input and a second input, both of which connect to selected ones of the amplifying elements. The digital-to-analog converter includes a first output that is in communication with the switch and the first input of the power amplifier chip. The digital-to-analog converter has a second output that is in communication with the switch, and the switch has an output that is coupled to the first input of the power amplifier chip through the selected amplifying elements. The switch therefore enables the tracking control IC system to have a wider dynamic range control voltage Vc without increasing the die area of the servo control chip, without adding external active components to the PCB, and without increasing the control signal's susceptibility to noise pickup or offsets.

Circuitry and methods for adjusting and switching the gain of a

A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in the two-wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.

Diagnostic system including a LSI or VLSI integrated circuit with a

An analog data acquisition system in an integrated circuit automatically processes and stores analog data without sequencing support from a processor. The analog data acquisition system converts each analog input signal into digital data. The digital data are stored in registers in the integrated circuit that are directly readable by a digital signal processor without data moves and are directly usable by the digital signal processor without further processing or conversion. Consequently, the analog data acquisition system minimizes the use of both the digital signal processor and the digital signal processor program memory and leaves capacity, i.e., both processing time and instruction memory locations, for use in other activities. The analog data acquisition system includes an analog input multiplexer and an analog-to-digital (A/D) converter that has an input line that is connected to the analog input multiplexer output line. An acquisition sequencer provides signals to the analog input multiplexer so that a signal on one of the plurality of input lines to the analog input multiplexer is applied to the A/D converter.

Analog data acquisition system

An integrated circuit includes a programmable servo burst sequencer that includes an instruction memory, an instruction register, and an address control circuit. The instruction register drives a plurality of output lines of the programmable servo burst sequencer. The programmable servo burst sequencer can process a plurality of fields in any one of a plurality of servo sectors. The programmable servo burst sequencer eliminates the need for a specific servo burst sequencer for each possible configuration of the plurality of fields in a servo sector. The user simply uses a plurality of instructions to configure the programmable servo burst sequencer so that the programmed servo burst sequencer can process the plurality of fields in the servo sector information on the user's disk drive.

Programmable servo burst sequencer for a disk drive

A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in said the wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.

Diagnostic data port for a LSI or VLSI integrated circuit

A disk drive controller integrated circuit includes a programmable servo burst decoder that can process any one of a plurality of servo sectors. A disk drive head reads each embedded servo sector on the disk and provides an analog signal, a servo burst, representing the servo sector to a preamp. The preamp provides an amplified analog signal to a read channel integrated circuit. The read channel integrated circuit provides input signals that are processed by the programmable servo burst decoder. The programmable servo burst decoder includes a programmable timing mark sequencer having an instruction register of a first size and a servo timing mark output line, and a programmable burst sequencer connected to the servo timing mark output line and having an instruction register of a second size. In this embodiment, the first size is different from the second size. Specifically, the first size is 20 bits, and the second size is 38 bits.

Growing community of inventors

Nederland, CO, United States of America

John P Hill