Intelligent Security Systems Corporation

Dallas Semiconductor Corporation

John P Heptig

George R Schultz

Robert F Anderson

Robert D Lee

Robert W Mounger

Robert Baker

A device and method is provided using a split processor based architecture to provide physical security of information by implementing a required protocol before releasing information. The information is used as a key to a cryptographic algorithm. A chaotic cryptographic algorithm is also provided including a key space employing six parameters of a Lorentzian system of equations.

Electronic encryption device and method

A device and method is provided using a split processor based architecture to provide physical security of critical information by implementing a required protocol before releasing critical information. The critical information is used as a key to a cryptographic algorithm. A chaotic cryptographic algorithm is also provided including a defined key space employing six parameters of a Lorenzian system of equations.

A system for controlling access to a computer. Memory-resident software logic cooperates with a remote electronic key device coupled to the computer's processor, through the printer port, to disable the computer unless an authorized key is inserted in the key device. The logic is executed in the processor responsive to the computer's system timer interrupt for continuous monitoring capability. Until a user inserts an authorized key, or upon removal of the key, the logic suspends operation of any application programs, the monitor is blanked and the mouse, keyboard and floppy disk drive are disabled. A record is stored in memory of authorized users and user audit information. Utility menu options are used to add or delete user keys, display access and usage records and to customize the number and selection of I/O devices to be disabled by the system.

Security access and monitoring system for personal computer

A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator. Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized. Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.

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Fort Worth, TX, United States of America

John P Heptig