Lucent Technologies Inc.

Lattice Semiconductor Corporation

American Telephone & Telegraph Co., At&t Bell Laboratories

John P Fishburn

William B Andrews

Harold Scholz

Alfred E Dunlop

Catherine Anne Schevon

Barry Britton

Yu-Chun Wu

Xiaotao Chen

Todd R Seigfried

Craig R Kemp

Sanjiv Taneja

An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay. The integer nonlinear program comprises a system of monotone difference constraints on finite integer ranges, and is solvable utilizing a modified Bellman-Ford algorithm.

Method and apparatus for controlling signal distribution in an electronic circuit

Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements 'steals' a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.

Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units

A method for calibrating a circuit analyzer includes determining a plurality of initial technology parameters characterizing the circuit according to a timing model of the circuit. A delay along an entire logic path of the circuit is expressed as a function of the technology parameters. A benchmark set of circuit paths is determined which has fixed topology, device sizes, and wire capacitances. The technology parameters are then optimized to minimize error over the set of circuit paths to obtain optimized parameters for use in the timing model. The optimized technology parameters minimize the average error for the benchmark set of paths relative to SPICE or physical measurements. Average error is significantly reduced on a representative set of paths when compared to the conventional approach of separately measuring each parameter.

Method and apparatus for calibrating static timing analyzer to path

In accordance with the invention, a conductive lead line extending between a source and a capacitance load has a width w(x) which is a function of the distance x. For many practical applications such as leads for multichip modules, w(x) can be taken as the exponential function of the distance from the load given by the equation below. For many applications w(x) can be adequately approximated by the first three terms of a power series representation: ##EQU1## where W.sub.0 is the width of the lead line at x=0, C.sub.0 is the load capacitance and C.sub.0 is the area capacitance. For VLSI applications w(x) is a friction which can be designated.noteq.E(W.sub.0, C.sub.0, C.sub.p, C.sub.S, x) where C.sub.p is the perimeter capacitance. E(W.sub.0, C.sub.0, C.sub.p, C.sub.S, x) is derived herein. For most practical applications, w(x) can be adequately approximated by the first three terms: ##EQU2## In contrast with optimal-width rectangular wire, the RC Elmore delay of the optimally tapered lead goes to zero as the driver resistance approaches zero.

Minimal delay conductive lead lines for integrated circuits

A system and method integrate mask layout tools to automate the generation of mask layouts for fabricating an integrated circuit corresponding to an input netlist and a timing specification. The mask layout is generated by the method including the steps of automatically sizing transistors specified in the netlist, clustering the sized transistors into cells, generating a cell library, and placing-and-routing the cells to generate the mask layout. The system includes associated memory and stored programs, including a plurality of mask layout tools; and a processor operated by an automatic mask layout generation program for sequentially applying the plurality of mask layout tools to generate the mask layout from the input data. The plurality of mask layout tools includes: a transistor sizing tool for sizing transistors and to generate a netlist; a cell library generation tool for generating a cell library from the netlist; a place-and-route tool for generating the mask layout; and optionally a clustering tool for clustering the netlist generated by the transistor sizing tool into a plurality of cells.

System and method for generating mask layouts

A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.

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Murray Hill, NJ, United States of America

John P Fishburn