Texas Instruments Corporation

John P Erdeljac

Louis N Hutter

Taylor R Efland

Jeffrey P Smith

Marco Corsi

John Kenneth Arch

Sameer P Pendharkar

Donald Charles Abbott

Chi-Cheong Shen

Charles E Williams

Konrad Wagensohner

Quang X Mai

M Ali Khatibzadeh

Walter Bucksch

Mary Ann Murphy

Henry Litzmann Edwards

Binghua Hu

Abbas Ali

Han-Tzong Yuan

James Robert Todd

Jozef C Mitros

Jau-Yuann Yang

Chin-Yu Tsai

Jarvis Benjamin Jacobs

Milton Lee Buschbom

C Matthew Thompson

James D Goon

Arnold C Conway

Shiu-Hang Yan

Britton Robbins

Mark E Gibson

AnhKim Duong

Susan S Kearney

A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.

Deep trench with self-aligned sinker

An integrated circuit device ( ) with a bonding surface ( ) directly over its active circuitry, and a method of making such integrated circuits (FIGS. A- E). To make the bonding surface ( ), a wafer ( ) is provided with vias ( ) to its metallization layer ( ) and then coated with a seed metal layer ( ). A plating pattern ( ) is formed on the wafer ( ), exposing portions of the seed metal layer ( ) and blocking the rest of the seed metal layer ( ). These exposed portions are plated with successive metal layers ( ), thereby forming a bonding surface ( ) having a number of layered stacks ( ) that fill the vias ( ). The plating pattern and the nonplated portions of the seed metal layer ( ) are then removed.

Integrated circuit with bonding layer over active circuitry

A tunnel diode construction for an EEPROM device , and method for making it are shown. A tank is provided at a surface of a semiconductor substrate containing a doped diffused tunnel region . A layer of insulation is provided over the surface of the substrate with a first thickness to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness elsewhere. A conducting floating gate is provided above the doped diffused tunnel region and at least part of the tank , on the layer of insulation . The floating gate extends over the oxide beyond the lateral boundaries of the doped diffused tunnel region in every direction to terminate over the second thickness of oxide over the tank . To complete the EEPROM device , an MOS transistor having source and drain doped regions provided in the substrate , with a portion of the floating gate capacitively coupled to a control gate and extending over at least part of a channel region of the MOS device.

Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region

An LDMOS device ( ) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells ( ). The Dwell ( ) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region ( ), which permits the n-type region of the Dwell to diffuse under the gate region ( ) an sufficient distance to eliminate misalignment effects.

LDMOS power device with oversized dwell

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Metalization outside protective overcoat for improved capacitors and inductors

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Power transistor with silicided gate and contacts

Metallization outside protective overcoat for improved capacitors and inductors

A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

Transistor with increased operating voltage and method of fabrication

An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).

Self aligned DMOS transistor and method of fabrication

A method of fabricating a semiconductor device containing a HVDMOS transistor and a LVDMOS transistor and the device which includes providing a region of semiconductor material of a first conductivity type and forming a high voltage DMOS transistor disposed in the region. A relatively low voltage DMOS transistor is also disposed in that region and electrically isolated from the high voltage DMOS transistor. The low voltage DMOS transistor has spaced apart source and drain regions disposed in the region of semiconductor material and a back gate region of the first conductivity type disposed in the region of semiconductor material between the source and drain regions. The back gate region is electrically coupled to the region of semiconductor material. The region of semiconductor material includes a surface, the source, drain and back gate regions extending to that surface. A well of second conductivity type opposite to the first conductivity type is provided in the region of semiconductor material and the high voltage DMOS transistor is disposed in that well. Optionally, one only of the source or drain regions of the low voltage DMOS transistor is disposed in the well. Also, optionally, a region of second conductivity type opposite to the first conductivity type can be provided between the back gate region and the drain region which is less highly doped than the drain region.

Low voltage DMOS transistor

A DMOS transistor (50) includes an Nwell (70); a Dwell (76) formed in the Nwell (70); a source region (78) formed in the Dwell (78), a channel region (80) defined between an edge of the source region (78) and an edge of the Nwell (70); a gate (86) extending over the channel region (80); and a p+ backgate contact region (90) formed in the source region (78) so as to counterdope and extend through a first portion of the source region (78) to contact the Dwell (76). The formation of the p+ backgate contact region through the source region (78) eliminates the need for a large annular shaped source region resulting in a considerable reduction in both device area and on-resistance.

DMOS transistor with low on-resistance and method of fabrication

A method for making an EEPROM (10) in a semiconductor substrate (40) and EEPROM made according to the method includes forming a gate dielectric (38), such as oxide, nitride, multilayer dielectric, or the like, on a surface of the substrate (40) and forming a polysilicon floating gate (19) on the gate dielectric (38). A control gate (25) is formed at least partially overlying the floating gate (19), and a thermal oxide layer (56) is formed on the floating gate (19) in regions that are not covered by the control gate. Thus, the thermal oxide layer (56) encases any regions of the floating gate (19) uncovered by the control gate (25) and serves as a high quality dielectric to isolate the floating gate (19) from charge loss and other deleterious effects. Then, source and drain regions (21,27) are formed in the substrate (40).

Method for making an EEPROM with thermal oxide isolated floating gate

A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Growing community of inventors

Plano, TX, United States of America

John P Erdeljac