Intel Corporation

John P DeVale

Bryan P Black

Edward A Brekelbaum

Jeffrey P Rupley, Ii

Donald W McCauley

Mohammed Hasan Taufique

Derwin Jallice

Gabriel H Loh

Murali M Annavaram

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Memory array on more than one die

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

Prefetching from dynamic random access memory to a static random access memory

A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.

Multi-purpose register cache

A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.

Growing community of inventors

Austin, TX, United States of America

John P DeVale