Intel Corporation

John P Barnak

Mark L Doczy

Justin K Brask

Jack T Kavalieros

Robert S Chau

Brian S Doyle

Chris E Barns

Steven J Keating

Michael L McSwiney

Matthew V Metz

Markus Kuhn

Ying Zhou

Ming Fang

Jacob M Jensen

Collin Borla

Robert L Bristol

Scott A Hareland

Kevin J Lee

Chunlin Liang

Mukul P Renavikar

Bryan J Rice

Melissa K Shell

Seshu V Sattiraju

Tzuen-Luh Huang

Margherita Chang

Gerald B Feldewerth

Harry Y Liang

Andrew W H Yeoh

Paul R Markworth

Michael Mcswiney

Passivation coatings and gettering agents may be used in an Extreme Ultraviolet (EUV) source which uses tin (Sn) vapor as a plasma 'fuel' to prevent contamination and corresponding loss of reflectivity due to tin contamination. The passivation coating may be a material to which tin does not adhere, and may be placed on reflective surfaces in the source chamber. The gettering agent may be a material that reacts strongly with tin, and may be placed outside of the collector mirrors and/or on non-reflective surfaces. A passivation coating may also be provided on the insulator between the anode and cathode of the source electrodes to prevent shorting due to tin coating the insulator surface.

Technique to prevent tin contamination of mirrors and electrodes in an EUV lithography system

At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Integrating n-type and p-type metal gate transistors

A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or 'tuned' depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

Methods of forming a multilayer stack alloy for work function engineering

Methods of forming a microelectronic structure are described. Those methods include forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer includes a coefficient of thermal expansion that is approximately between the coefficient of thermal expansion of the first adhesion layer and the coefficient of thermal expansion of the barrier layer.

Forming an intermediate layer in interconnect joints and structures formed thereby

Apparatus and methods of fabricating an under bump metallization structure including an adhesion layer abutting a conductive pad, a molybdenum-containing barrier layer abutting the adhesion layer, a wetting layer abutting the molybdenum-containing barrier layer, and high tin content solder material abutting the wetting layer. The wetting layer may be substantially subsumed in the high content solder forming an intermetallic compound layer. The molybdenum-containing barrier layer prevents the movement of tin in the high tin content solder material from migrating to dielectric layers abutting the conductive pad and potentially causing delamination and/or attacking any underlying structures, particularly copper structures, which may be present.

Under bump metallization layer to enable use of high tin content solder bumps

An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type. In a particular embodiment, an integrated circuit includes an n-channel FET having a tantalum-based gate electrode with a work function approximately the same as n-doped polysilicon, and a p-channel FET has a tantalum nitride-based gate electrode with a work function approximately the same as p-doped polysilicon.

MOSFET gate electrodes having performance tuned work functions and methods of making same

integrating n-type and P-type metal gate transistors

A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

Method for making a semiconductor device having a high-k gate dielectric

A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

A method for making a semiconductor device is described. That method comprises forming on a substrate a high-k gate dielectric layer that includes impurities, then forming a silicon containing sacrificial layer on the high-k gate dielectric layer. After the silicon containing sacrificial layer has gettered the impurities from the high-k gate dielectric layer, the silicon containing sacrificial layer is removed, and a gate electrode is formed on the high-k gate dielectric layer. The method optionally includes exposing the high-k gate dielectric layer to a silicic acid containing solution until a silicon dioxide capping layer forms on the high-k gate dielectric layer, prior to forming a gate electrode on the capping layer.

A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

Precise patterning of high-K films

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Beaverton, OR, United States of America

John P Barnak