Seagate Technology Incorporated

John Oliver Burness

Richard Franklin Lary

A hierarchical compression tester and associated method employs a grid-based storage capacity wherein a storage unit is defined by a grouping of data blocks. Each data block is stored in one of a plurality of storage devices. Each stored data block has a data portion and a data integrity field (DIF) including a data reliability qualifier (DRQ) indicating whether the respective data portion is valid. The tester also has a logical device allocation map that includes a storage unit descriptor array that identifies one or more storage units corresponding to a selected logical address. The logical device allocation map has a DIF array that identifies whether any of the data blocks in the one or more storage units corresponding to the selected logical address includes invalid data.

Hierarchical data compression testing

An apparatus and associated method are provided whereby first and second spindles operably rotate first and second overlapping storage discs, respectively. First and second data transfer members are operably disposed adjacent storage areas of the respective storage discs. An edge of the first disc moves in a prescribed close spatial separation from a rotating surface of the second spindle so that the second spindle strips windage, generated by the rotation of the first disc, away from the second data transfer member.

Windage control in a dual spindle storage device having interleaved storage media

Method and apparatus for providing a visual indication of operational activity of a device, such as a selected data transfer state. A pattern generator provides one or more bitmasks, each comprising a selected multi-bit sequence of logical values. A switching circuit selectively activates a visual indicator, such as a light emitting diode (LED), to provide a different visual indication in relation to each bitmask. Preferably, a time-varying rate at which the visual indicator is activated in response to each bitmask is selected to be different from a rate, as perceived by a human observer, of activation of the indicator. The pattern generator is preferably implemented as a programming module in a memory space and executed by a processor. Alternatively, the pattern generator is implemented in hardware preferably through the use of an index table and shift register circuitry.

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Colorado Springs, CO, United States of America

John Oliver Burness