Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

John O'Dowd

Damien Joseph McCartney

Eamon Hynes

William Hunt

John M Wynne

Jochen Schmitt

Jan Kubik

Oliver J Kierse

Stephen O'Brien

Peter James Tonge

Monsoon Dutt

Gabriel Banarie

Enda Joseph Nicholl

Robert Guyol

Aude Richard

Brian O'Mara

Wenmei Wang

Peter G Meehan

Michael Mueller-Aulmann

Colin P Giles

Christian Nau

John R Martin

Tadhg Creedon

Kevin Jennings

Thomas J Meany

Tomas Tansley

Patrick G Crowley

Nicola M O'Byrne

Adam Glibbery

Michal Brychta

Niall McGuinness

John Keane

Damien Mccartney

Damien Mccarthy

A magnetic sensor package comprising a magnetic multi-turn sensor die and a magnetic single turn sensor die, in which both sensor dies are packaged on the same lead frame. A method of manufacturing the magnetic sensor package is also provided. A magnetic sensor system comprising a rotating magnet and the magnetic sensor package, where the sensor package is arranged so that both sensor dies sit within a homogenous magnetic field, thereby ensuring that the output signal of each sensor is not corrupted by any stray fields.

Magnetic sensor package and magnetic sensing system

Magnetic sensor package

In an isolation system, different analog to digital converters ('ADCs') are provided on a first side of an isolation barrier. Outputs from the ADCs may be merged into a common data stream and communicated across the isolation barrier by a single isolation device. The ADCs may sample independent signals or may sample a common signal. When the ADCs sample a common signal, the system may monitor the input signal for fault conditions. During no fault operation, results of an analog-to-digital conversion may be communicated across an isolation barrier by an isolation device. During a fault condition, data representing the fault condition may replace the ADC data in communication across the isolation barrier. Fault conditions may be signaled by unique data patterns that can be distinguished from ADC data.

Isolator system supporting multiple ADCs via a single isolator channel

A sealed capacitive sensor includes a substrate having a diaphragm forming a first plate of a capacitor; a second fixed plate of the capacitor spaced from the diaphragm and defining a predetermined dielectric gap and a sealing medium connecting together the substrate and fixed plate in an integrated structure and hermetically sealing the gap.

Sealed capacitive sensor

Proximity detection is accomplished by determining with a moving average calculation a moving average level of input data; setting a threshold level in response to the average level and a sensitivity factor; producing a proximity detection output when the input data meets the threshold level; and changing the weighting used by the average level calculation in response to a proximity detection output.

Proximity detection system and method

A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.

Spaced, bumped component structure

Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.

Automatic range shift system and method for an analog to digital converter

A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Capacitive sensor

A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.

One terminal capacitor interface circuit

A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.

A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Reduced chop rate analog to digital converter system and method

A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Variable capacitance switched capacitor input system and method

A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to V,and charge corresponding to &Dgr;V,to a summing node of the charge balance circuit, where V,is a voltage produced across a p-n junction and where &Dgr;V,is a difference between two V,voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to V,and charge corresponding to &Dgr;V,are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output. Thus, the reference sampling and charge transfer circuit delivers V,and &Dgr;V,charge samples to the summing node having the correct proportion and polarity, that in aggregate over a modulator cycle, equal the charge that sampling the reference voltage V,produced by the explicit bandgap reference circuits would deliver.

Bandgap reference circuit for charge balance circuits

An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Method of invoking a power-down mode on an integrated circuit by

A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.

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Crecora, Ireland

John O'Dowd