Applied Micro Circuits Corporation

John Ngai

Alfred Yeung

Hamid Partovi

Luca Ravezzi

Ronen Cohen

A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.

Shadow latch

Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.

Pseudo single-phase flip-flop (PSP-FF)

A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.

Pass gate shadow latch

A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a Dsignal, an input to accept a clock signal, an input to accept an inverted shadow-Dsignal, and an output to supply a Dsignal. The master latch has an input to accept a shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Dsignal and the inverted shadow-Dsignal. The slave latch has an input to accept the Dsignal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the Dsignal or the shadow-Dsignal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.

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John Ngai