International Business Machines Corporation

John N Hryckowian

Jack A Dorler

Ray Raphy

Dennis C Banker

Charles Kyriakos Vakirtzis

Alan Daniel Stigliani

Heidi L Lagares-Vazquez

Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in launch/capture clocking systems are provided, whereby the A/B/C (test/launch/capture) clock wire nets are designed using a five parallel track wire segment, in which the B clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, the C clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, and where the A test clock wire is represented as a single track comprising test signal wire disposed between the B and C signal wires.

Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.

Complementary cascoded logic circuit

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Raleigh, NC, United States of America

John N Hryckowian