Cisco Technology, Inc.

Ericsson Gmbh

John Mitten

William Robert Lee

Kenneth Harvey Potter, Jr

David Richard Barach

Jeffery B Scott

Kent H Hoult

Christopher G Riedle

Earl R Wingrove

Kenneth H Potter

Trevor Garner

Martin Hughes

Robert Leroy King

Sriram Haridas

Randall Glenn Bright

Techniques for initializing an arbitrary portion of memory with an arbitrary pattern includes using a memory controller for performing sequenced read and write operations. The memory controller receives address data, length data and pattern data on a data bus connected to a processor. The address data indicates a location in memory. The length data indicates an amount of memory to be initialized. The pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data. The memory controller performs multiple write operations on memory beginning at a first location based on the address data and ending at a second location based on the length data. Each write operation writes the pattern data to a current location in memory, thereby initializing the arbitrary portion of memory with an arbitrary pattern based on the pattern data.

Method and apparatus for arbitrarily initializing a portion of memory

A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.

System and method for communicating in a multi-processor environment

A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a 'free' buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.

Hypertransport data path protocol

A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To that end, a buffer manager controls access to a set of 'free' buffer descriptors, each free buffer descriptor referencing a corresponding buffer in the set of data buffers. Advantageously, the buffer manager ensures that the first and second devices are allocated a sufficient number of free buffer descriptors for use in a HPT data path protocol in which the first and second devices have access to respective sets of free buffer descriptors. Because buffer management over the HPT bus is optimized by the buffer manager, the amount of processing bandwidth traditionally consumed managing descriptors can be reduced.

Buffer management technique for a hypertransport data path protocol

A method for decrementing a reference count in a multicast environment is provided that includes receiving an access request for a particle stored in a memory element. The memory unit is then accessed in response to the access request, the particle being read from the memory element. The particle includes a plurality of data segments, a selected one or more of which includes a first reference count associated with the particle. The particle is then presented to a target that generated the access request. The first reference count associated with the selected one or more data segments is then decremented in order to generate a second reference count. At least one of the plurality of data segments with the second reference count is then written to the memory element.

System and method for decrementing a reference count in a multicast environment

An electronic device includes an indicator that generates an indication of an event responsive to an indicator control signal from an indicator control circuit coupled between a processor and the indicator. The processor generates an indicator off-time value and an indicator on-time value from the processor. The indicator control circuit includes an off-time register, an on-time register, and an indicator control circuit. The off-time register stores the off-time value generated by a processor, and the on-time register stores the on-time value generated by the processor. The indicator control signal generator alternatingly enables and disables the indicator control signal based on the time values stored in the registers.

Electronic devices including indicator control circuits and related methods of controlling indicators

Integrated circuit transmit modules include an integrated circuit substrate, a baseband I/Q modulator in the integrated circuit substrate that modulates an input signal to produce in-phase (I) and quadrature (Q) baseband modulated inputs, and a built-in self-test (BIST) module in the integrated circuit substrate that monitors the I and Q baseband modulated outputs, to determine whether the baseband I/Q modulator is operating properly. The BIST module generates test input data for the baseband I/Q modulator. Alternatively or in addition, the BIST module can monitor the I and Q baseband modulated outputs in response to a communications input signal from a digital signal processor. The BIST module can generate a status signal to indicate whether the baseband I/Q modulator is operating properly. The BIST module includes a first filter that is responsive to the input signal to produce a filtered input signal and a second filter that is responsive to the I and Q baseband modulated outputs, to produce a filtered output signal. A compare module compares the filtered input signal and the filtered output signal. A phase and amplitude adjuster adjusts the phase and/or amplitude of the output of the first filter. Accordingly, modulators are tested prior to and/or during field use.

Built-in self-test systems and methods for integrated circuit baseband quadrature modulators

An electronic device includes an indicator that generates an indication of an event responsive to an indicator control signal from an indicator control circuit coupled between a processor and the indicator. The processor generates an indicator off-time value and an indicator on-time value when an indication is desired, and the indicator control circuit receives the indicator off-time value and the indictor on-time value from the processor. More particularly, the indicator control circuit includes an off-time register, an on-time register, and an indicator control circuit. The off-time register stores the off-time value generated by the processor, and the on-time register stores the on-time value generated by the processor. The indicator control signal generator alternatingly enables the indicator control signal for a period of time determined by the on-time value stored in the on-time register and disables the indicator control signal for a period of time determined by the off-time value stored in the off-time register. The electronic device can also include an indicator pulse-duty register and a pulse width modulation circuit. The indicator pulse-duty register can be coupled to the processor and store an indicator pulse-duty generated by the processor. The pulse width modulation circuit can be coupled to the indicator pulse-duty register wherein the pulse width modulation circuit modulates a pulse width of the enabled indicator control signal in response to the indicator pulse-duty stored in the indicator pulse-duty register.

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Cary, NC, United States of America

John Mitten