Texas Instruments Corporation

John Millard Caywood

Al F Tasch, Jr

Robert T Bate

The specification discloses a read only memory constructed from a charge coupled device having a channel for storage of charges in bit regions defined along the channel. Various structures are disclosed for storing combinations of two different levels of charge in the bit regions. In one embodiment, storage gates which communicate at spaced points along the length of the CCD channel are provided with different widths to control the level of charge input by the storage gates to the channel bit regions. In alternate embodiments, the semiconductor doping or oxide thickness of the storage gates are controlled in order to cause different levels of charge to be stored in the channel gate bit regions. After storage of the different charge levels in the channel, phase electrodes which span the channel are operated to serially output the charge levels from the channel to provide a predetermined digital word.

Read only memory utilizing charge coupled device structures

An input scheme suitable for low-level input signals, e.g., from an IR detector array, wherein the input signals are transferred over respective channels to parallel inputs of a charge transfer device shift register, under control of IGFET switching transistor circuits in each channel. Corresponding IGFETS in the channels are operated by common gate voltages. Introduction of noise due to variation of the gate threshold voltages between IGFETS in the transfer circuits is obviated by using the same IGFET in each channel to reset the potential at the input node of that channel as well as to transfer the input signals over that channel to the shift register.

Charge transfer device signal processing

The specification discloses a three level electrode configuration for a charge coupled device having a channel for movement of charge packets therethrough. The configuration includes three spaced apart phase buses disposed parallel along one side of the channel. Sets of phase electrodes extend from each of the phase buses across the channel. Adjacent ones of the phase electrodes from different phase buses are formed on different levels and have laterally offset and overlapping edges. Insulation layers are disposed between the phase electrodes on different levels.

Three level electrode configuration for three phase charge coupled device

The disclosure relates to a system for controlling the total charge collected on a charge-coupled imager to, in effect, provide an electronic shuttering action for the charge-coupled imager. The charge-coupled imager works in standard fashion and is normally biased into depletion whereby minority carriers, generated by the light impinging on the imager, are collected in predetermined charge collecting areas or wells, the charges in each well then bring read out in a serial fashion. In order to prevent collection of an excess number of charges, which is equivalent to overexposure in a photographic sense, the majority carriers which are necessarily generated simultaneously with the minority carriers, are collected and integrated so that when a predetermined amount of charge is measured, a shuttering action can take place. When the basic imager is formed from p-type silicon, the majority carrier charges are collected by providing an ohmic contact to the p-type substrate. Two modes ofoperation are disclosed. The first mode is suitable for imaging applications and the second mode is suitable for laser warning receivers.

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Richardson, TX, United States of America

John Millard Caywood