Conexant Systems, Inc.

John Milford Brooks

Brett Bernath

Manoj Mehta

Yoav Pesach Goldenberg

Moshe Goldenberg

Matthew J DiMeo

Manhar Karsanbhai

Steven S Mair

Daniel A Marotta

A raster to block converter and equivalently a block to raster converter can be implemented using enough memory to contain a single image band, that is a band of pixels of height equal to a single block but spanning the entire width of an image. The raster to block converter can operate at full rate so that as soon as a pixel is read out from the memory a new pixel can be stored in its place. The location of a pixel can be tracked using a mapping involving basic modular arithmetic. This raster to block converter is scalable so that it can work with any size image and block size.

Systems and methods for raster-to-block converter

A communication device such as a cable modem that has a first interface for receiving data from a cable media, and a pattern matching engine that evaluates patterns in the data that is received at the first interface of the cable modem and that enables the determination of appropriate procedures for treatment of the data. The pattern matching engine of the cable modem may be configured to match address segments of the data that is received at the first interface of the cable modem. In addition, the pattern matching engine is often a programmable pattern matching engine that may be programmed according to patterns that are desired to matched during various operations of the cable modem. Of note, the pattern matching engine enables pattern matching of various length frame portions. Various aspects of the present invention may also be found in a method for a communication device to compare a predetermined pattern to a pattern that corresponds to a portion of a data frame. The method includes determining acceptable parameters for the data frames that are to be received at the communication device; programming the acceptable parameters into a pattern matching engine in the communication device; receiving a data frame at the communication device; parsing the data frame to obtain a predetermined portion of the data frame; comparing the predetermined portion of the data frame with the acceptable parameters stored in the pattern matching engine; and registering the result of the comparison in a suitable format for access by a microprocessor.

Programmable pattern match engine

A cable modem having a programmable media access controller (MAC). A single cable modem device includes all necessary MAC functions. The invention allows programmable MAC functions to support evolving standards (e.g., DOCSIS) without requiring expensive hardware upgrades. Bifurcated microprocessor architecture, in which first processing circuitry is programmed to implement MAC functionality for processing information flowing to and from cable media interface circuitry, and second embedded processor core or host system processor provides operating system functionality are used. Alternatively, separate processor cores provide MAC functionality for downstream and upstream data paths, respectively. Cable media interface circuitry, and other peripheral circuitry, are coupled to a peripheral bus that is linked by a bridge circuit to a system bus. The processing circuitry MAC is communicatively coupled to the system bus. Centralized DMA control directs data transfer between the peripheral and system buses as determined, at least in part, by the programmable MAC.

Cable modem having a programmable media access controller

A method for detecting dropouts in digital data transferred over a bus from a digital data source to a computer system. Each address in the computer system buffer memory is initialized to a selected code value known not to exist in the data to be transferred. After sequential transfer of data to the buffer memory, the presence of the selected code value in the buffer memory indicates that a dropout occured.

Method for detecting dropouts in data delivered over a bandwidth-limited bus

A communication device, such as a cable modem, having a programmable media access controller (MAC) supported by a programmable CRC engine. The CRC engine computes CRC values for data written to it by the programmable MAC or other software process, thereby relieving processing circuitry of these computationally burdensome functions. The programmable nature of the CRC engine permits compliance with a wide variety standards, including evolving standards such as DOCSIS, without requiring expensive hardware upgrades. In one embodiment of the invention, the CRC engine may be initialized by the programmable MAC with an initial vector prior to CRC computations. The programmable MAC or other software then locates the data bytes (e.g., data frame header data) for which a CRC is to be computed. This information is written to a data register of the CRC engine and a CRC operation is performed. Based on the results, the programmable MAC may determine whether the CRC operation indicates valid data. For example, the CRC value may be compared to value communicating a frame header for purposes of validating received data frames. The CRC engine may advantageously utilize one or more polynomials as determined by the programmable MAC. Further, the CRC engine of the disclosed embodiment may receive data of varying sizes such that write processes may be optimized.

Single clock cycle CRC engine

A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Method and apparatus for upstream burst transmission synchronization in cable modems

An electronic bridging device for transferring electronic data between a first device attached to a system bus and a peripheral device attached to a peripheral bus using a bridging circuit. The DMA controller comprises a system bus interface circuit for connecting the DMA controller to the system bus, a peripheral bus interface circuit for connecting the DMA controller to the peripheral bus, a data transfer request circuit for receiving data transfer requests from devices attached to the peripheral bus, and a control logic circuit for controlling the operation of DMA data transfer operations. Immediately upon receipt of one or more data transfer requests, the bridging device performs the following operations: requests access to the system bus, concatenates all pending peripheral bus data words into a single transfer, and transfers all pending requests across the bridging circuit. A corresponding method of transferring electronic data between a first device attached to a system bus and a peripheral device attached to a peripheral bus using a bridging circuit having a DMA controller is disclosed. The method comprises receiving one or more data transfer requests from devices attached to the system bus and the peripheral bus, immediately requesting access to the system bus upon receipt of the data transfer requests by the DMA controller, concatenating all pending peripheral bus data words into a single transfer sequence, and transferring all pending requests across the bridging circuit.

Asochronous centralized multi-channel DMA controller

Method and apparatus for upstream burst transmissions synchronization in cable modems

An electronic bridge for providing a first electronic device attached to a high-data throughput bus and a second electronic device attached to a peripheral bus. The bridge further has an output bus circuit for generating output bus signals onto the peripheral bus, the output bus comprising a peripheral data bus a peripheral address bus. The bridge also has an output size signal circuit for generating output size signals for indicating the number of bits being used for a data transfer over the peripheral data bus, and an output control signal circuit for generating a output control signals onto the peripheral bus. The plurality of output control signals comprise, a PWRITE write control signal for indicating whether a write operation is occurring, a continuous PCLK clock signal having a rising edge and a falling edge for controlling the transfer of data over the lower-speed peripheral bus, and one or more PSELx signals for indicating the particular cycle of the PCLK signal in which data is to be transferred over the lower-speed peripheral bus. A corresponding slave apparatus for transferring digital data from a first electronic device attached to a high-data throughput bus through an electronic bridging device to a lower-speed peripheral bus. The slave apparatus has an input bus for receiving a plurality of output bus signals from the peripheral bus, an input size signal circuit for receiving output size signals for indicating the number of bits being used for a data transfer over the peripheral data bus, and an input control signal circuit for receiving input control signals from the peripheral bus.

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San Diego, CA, United States of America

John Milford Brooks