Cadence Design Systems, Inc.

John Michael MacLaren

Anne Hughes

Carl Nels Olson

Thomas J Shepherd

Anne Espinoza

Landon Laws

Jerome J Johnson

Bikram Banerjee

Jeffrey Scott Earl

Davika Raghu

Sreenivasan Kandagatla

Devika Raghu

Embodiments include herein are directed towards a double data rate ('DDR') controller system. Embodiments may include a plurality of read data buffers, wherein each of the plurality of read data buffers is configured for read data storage and is of a same size. Embodiments may further include a port read response queue that stores information corresponding to an incoming read and a command queue configured to receive read data buffer state information from the port read response queue. Embodiments may also include a read data buffer allocation tracker configured to track a state of each of the plurality of read data buffers.

System and method for memory management

Embodiments include herein are directed towards a dynamic random access memory system. Embodiments may include a command queue that is configured to hold all commands that are currently selectable for bank operation and execution. Embodiments may further include bank logic operatively connected with the command queue. The bank logic may include a bank management module and a plurality of bank slices, wherein each of the plurality of bank slices is an independent, re-assignable bank tracking module.

A multi-controller memory system includes a flexible channel memory controller coupled to at least first and second physical interfaces. The second physical interface is also coupled to an auxiliary memory controller. The physical interfaces may be coupled to separate memory modules. In a single-channel control mode, the memory controllers respectively control the memory modules coupled to the first and second physical interface. In a multi-channel control mode, the flexible channel memory controller controls both memory modules while the auxiliary memory controller is inactive. In a single-channel control mode, the memory controllers coordinate restricted memory control commands which access a resource shared by both modules, by one controller transmitting a request signal for the resource to the other controller, awaiting an acknowledgment signal from the other controller, and maintaining transmission of the request signal until the use of the resource is completed.

Variable channel multi-controller memory system

Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.

Caching error checking data for memory having inline storage configurations

A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.

System and method for memory control having selectively distributed power-on processing

Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.

Memory command interleaving

Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.

Multi-channel memory interface

Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.

Address failure detection for memory devices having inline storage configurations

A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.

Programmable, area-optimized bank group rotation system for memory devices

A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.

System and method for adaptively optimized refresh of memory

A system and method are provided to control error-protected access to a memory device having address integrity protection for data words of memory transactions. A communication port receives a command having a port address, which is adaptively converted to a memory address by an interface portion. The interface portion includes an adaptation stage carrying out a predefined adaptation response on an address propagated therethrough during a clock cycle of operation. An address protection portion configures the adaptation stage to maintain the predefined adaptation response over at least two clock cycles. Address error is detected based on comparison of output addresses respectively generated upon iterative propagation of the same input address through the adaptation stage over the clock cycles. A command control portion executes to adaptively split each command received from the interface portion, as well as the corresponding memory address according to an inline storage configuration of the memory device.

System and method for memory control having address integrity protection for error-protected data words of memory transactions

Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.

Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory

A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.

System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations

A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment's storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.

System and method for memory control having self writeback of data stored in memory with correctable error

An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

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Austin, TX, United States of America

John Michael MacLaren