International Business Machines Corporation

Motorola Corporation

John Michael Kaiser

Ravi Kumar Arimilli

Warren Edward Maule

John Steven Dodson

Jerry Don Lewis

William Kurt Lewchuk

Michael Scott Allen

Derek E Williams

David Wayne Victor

Sanjay Raghunath Deshpande

Joe C St Clair

Robert Dominick Mirabella

Loyal D Youngblood

Robert George Schaaf

A method of extending a cache of a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. A value is loaded from system memory into one or more caches of adjacent processing units, and when a requesting processing unit issues an inquiry onto the system bus to read the value, the value is sourced from the cache of the adjacent processing unit containing a copy of the value that was most recently accessed. Each cache has at least one cache line with a block for storing the value, and an indication is provided that a cache line having a block which contains an instruction or data is in a &ldquo;recently read&rdquo; state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). Any caches containing a valid copy of the value, other than the cache which contains a copy of the value that was most recently accessed, are assigned a state indicating that they hold the valid copy in a shared state. This protocol allows instructions and data which are shared among several caches to be sourced directly (intervened) by the cache having the most recently accessed copy, without retrieval from system memory (RAM), significantly improving the processing speed of the computer system.

Cache-coherency protocol with recently read state for extending cache horizontally

The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations

A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

Queued arbitration mechanism for data processing system

An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto. The system further includes means in a processor for building a queue of command blocks related to the auxiliary function processor, writing one or more command blocks to memory, which may include a processor cache, writing a start address for each command block to an address FIFO associated with the auxiliary function processor, reading a command block queue start address by the auxiliary processor, recognizing the command block read, issuing a coherent read for queued command blocks with intervention enabled, flushing a copy of the queued command block from processor cache to memory subsystem if a copy of the queued command block is in processor cache, intercepting the flushed copy of the queued command block from cache to memory and canceling the read to memory, storing the queued block in a command buffer associated with the auxiliary function processor, processing the commands in the queue by the auxiliary function processor, and writing a complete status to a predetermined location which is periodically polled by a processor on completion of the auxiliary function processing. For each data request to or from storage from the auxiliary function processor, a determination is made as to whether the request is for a coherent or non-coherent read or write of the data. If the request is for a non-coherent read or write, the snoop cycle on the processor bus is inhibited and bypassed since there is no need to perform a snoop to maintain coherency for non-coherent data. That data request is then handled and processed.

Information handling system including non-disruptive command and data movement between storage and one or more auxiliary processors

A method and apparatus for preventing the occurrence of deadlocks from the execution of variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. Execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others. The snoopers initiate operations at the same time based upon a common predefined event and ensure the operations end are finished concurrently when no outstanding retry operations are detected.

Method and apparatus for executing variable delay system bus operations of differing type or character without dead lock using shared buffers

The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of singly-initiated singly-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Method and apparatus for executing singly-initiated, singly-sourced variable delay system bus operations of differing character

An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, and to an I/O bus. Data management unit also includes interrupt routing logic which snoops interrupt packets, stores the information in registers, and generates a signal indicating whether a particular interrupt was accepted or rejected. If the interrupt logic has a higher priority interrupt pending, the current interrupt packet will be returned to the requesting device using the interrupt return transaction, and the requesting device will accept the return transaction by decoding the bus unit ID field in the packet. The interrupt will be requeued and held in a pending status until an interrupt reissue transaction is transmitted by the interrupt routing logic and received by the interrupting I/O controller. Interrupts may be generated by any I/O device connected to any of I/O controllers on the I/O bus, or by a high speed I/O device connected to processor address bus.

Handling interrupts by returning and requeuing currently executing

In multi-processor systems which have separated the system bus from the I/O bus, a Shadow Directory is introduced into the memory controller for reducing bottlenecks that occur from the processors snooping data cache in the I/O devices residing on the I/O bus. This Shadow Directory is advantageously employed in a system, such as the PowerPc architecture which distinguishes between the types of data that can be cached in I/O devices. The Shadow Directory uses two First In First Out (FIFO) stacks for two different types of data. These FIFO stacks are then used for addresses placed on the system bus and I/O bus in order to reduce snoop latency times.

Method and apparatus for reducing system snoop latency

A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a 'recently read' state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache. Upon sourcing the instruction or data value, the cache that originally contained the most recently accessed copy thereof changes its indication to indicate that its copy is now shared, and the processing unit which accessed the instruction or data value is thereafter indicated as having the cache containing the copy thereof that was most recently accessed. This protocol allows instructions and data values which are shared among several caches to be sourced directly (intervened) by the cache having the most recently accessed copy, without retrieval from system memory (RAM), significantly improving the processing speed of the computer system.

Cache-coherency protocol with recently read state for data and

In a data processing system including a bus connected to a plurality of devices capable of driving said bus, error reporting and isolation is achieved by signaling a self-check to each device connected to the bus to determine if it was driving the bus at the time an error occurred. The bus check request is generated by one of the devices connected to the bus in response to detecting either a parity error or an internal error. If a parity error is detected, a bus check request is signaled to a combining unit connected to the bus. The combining unit signals the self-check to each of the devices attached to the bus in response to receiving the bus check request. Each device determines whether it was driving the bus at the time the error occurred and, if so, sets a source of error indicator on the device. Similarly, if an internal error is detected, the detecting device sets source of error and internal error indicators on the detecting device and signals a bus check request to the combining unit. The source of error and internal error indicators are accessible to a machine check or service processor mechanism in the data processing system.

Fault isolation feature for an I/O or system bus

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, and the cache transmits a response indicating that the cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be improved substantially with this new protocol.

Cache intervention from a cache line exclusively holding an unmodified

A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a 'check stop' signal. Once frozen, the shift register can be scanned for fault isolation analysis.

Method for isolating faults on a clocked synchronous bus

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The specific cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

Shared intervention protocol for SMP bus using caches, snooping, tags

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address of a memory device of the computer system, and each cache snoops the interconnect to detect the message. Each cache thereafter transmits a response to the message, the response selected from the group consisting of an invalid response, a modified intervention response, a shared intervention response, or an alternative response, wherein the invalid response indicates that a cache does not contain any value corresponding to the address of the memory device, the modified intervention response indicates that a cache contains and can source a modified value corresponding to the address of the memory device, and the shared intervention response indicates that a cache contains and can source an unmodified value corresponding to the address of the memory device. A priority can be associated with each response from each cache, and the responses detected by system logic, the system logic forwarding a selected one of the responses to the requesting processing unit based on the highest priority response. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

Growing community of inventors

Cedar Park, TX, United States of America

John Michael Kaiser