Arm Limited

John Michael Horley

Michael John Williams

Paul Anthony Gilkerson

Andrew Brookfield Swaine

Michael John Gibbs

Edmond John Simon Ashfield

Simon John Craske

Thomas Sean Houlihane

Sheldon James Woodhouse

Alasdair Grant

Richard Roy Grisenthwaite

Thomas Christopher Grocutt

François Christopher Jacques Botman

Daryl Wayne Bradley

Stephan Diestelhorst

Anitha Kona

Katherine Elizabeth Kneebone

Christopher Neal Hinds

Andrew Christopher Rose

Simon Andrew Ford

Graeme Peter Barnes

Alastair David Reid

Ashley John Crawford

Christopher Vincent Severino

Nebojsa Makljenovic

Mark Salling Rutland

George James Milne

Paul Robert Gotch

Sheshadri Kalkunte

Uma Maheswari Ramalingam

Dan Brook

Ian William Spray

Michaell John Williams

Paul Gilkerson

Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.

Profiling of sampled operations processed by processing circuitry

Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

Writing beyond a pointer

A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

Technique for collecting state information of an apparatus

An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.

Apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry

To access metadata when debugging a device, debug access port circuitry including a debug interface receives commands from a debugger, and a bus interface coupled to a bus enables the debugger to access a memory system of the device. The device operates on data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus. The debug access port circuitry has storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. A metadata storage element stores metadata items, and the debug access port circuitry is responsive to a command from the debugger to perform a memory direct access to transfer metadata items between the metadata storage element and the memory system.

Apparatus and method for accessing metadata when debugging a device

Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

Register-provided-opcode instruction

An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.

Apparatus and method for controlling assertion of a trigger signal to processing circuitry

An apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, where the sequence of instructions comprises branch instructions. Trace generating circuitry generates a trace stream of trace items indicative of the data processing operations. The trace generating circuitry is responsive to one or more not-taken branch instructions followed by a taken branch instruction in the sequence of instructions to: include at least one not-taken trace item corresponding to the one or more not-taken branch instructions followed by a taken trace item in the trace stream when a current status condition of the apparatus is met, and to include a source address associated with the taken branch instruction in the trace stream when the current status condition of the apparatus is not met. A hybrid approach between tracing not-taken branch instructions and tracing a source address associated with the taken branch instruction is thus provided.

Tracing branch instructions

A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Trace data

An apparatus has an input interface for receiving instruction execution information from processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream. The instruction sequence from the processing circuitry includes at least one branch-future instruction that effectively turns an instruction identified by the branch-future instruction into a branch, and in particular causes the processing circuitry to branch to a target address identified by the branch-future instruction when that identified instruction is encountered within the instruction sequence. A branch control cache is used to store branch control information derived from the branch-future instruction, and the trace generation circuitry is arranged to detect, based on that branch control information, when the identified instruction has been encountered by the processing circuitry, and upon such detection to then issue within the trace stream a trace element to indicate that a branch to the target address has occurred.

A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items. The number of metadata items accessed by each instance of the metadata access operation is non-deterministic by the debugger from the metadata access operation. However, the at least one command is such that the plurality of instances of the metadata access operation are performed by the processing circuitry without the debugger interrogating the processing circuitry between each instance of the metadata access operation to determine progress in the number of metadata items accessed. Such an approach can significantly improve the efficiency of performing such accesses to metadata items under debugger control.

Method of accessing metadata when debugging a program to be executed on processing circuitry

An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.

Tracing the data processing activities of a data processing apparatus

There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

Apparatus and method to generate trace data in response to transactional execution

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

Counter circuitry and method

An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation. The apparatus has trace generation circuitry to generate from the execution information a data trace stream comprising a plurality of trace elements. For each predicated vector memory access instruction executed, the trace generation circuitry is arranged to issue within the data trace stream a number of address trace elements, each address trace element providing an address indication for an address accessed in memory, and each address trace element being associated with a fixed sized data block irrespective of the size of the data values accessed when executing the memory access instruction. The trace generation circuitry further issues within the data trace stream, for each predicated vector memory access instruction executed, at least one predicate trace element to identify any lanes of the vector that have been omitted from the memory transfer operation. It has been found that such an approach provides a particularly bandwidth efficient mechanism for tracing predicated vector memory access instructions.

Apparatus and method for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry

Growing community of inventors

Cambridge, United Kingdom

John Michael Horley