Agere Systems Inc.

Lucent Technologies Inc.

John Michael Hergenrother

Donald Paul Monroe

Pranav Kalavade

Yih-Feng Chyan

Yi Ma

Muhammed Ayman Shibib

Shuming Xu

Gary Robert Weber

Zhijian Xie

Hongzong Chew

An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.

Architecture for circuit connection of a vertical transistor

A diffused MOS device comprises one or more strained silicon portions formed in a carrier transit path of the DMOS device. The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path is at least partially defined by a body of the DMOS device, and may also include other regions, such as a diffusion area, channel region, or accumulation region. The one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed as a layer throughout. The one or more strained silicon portions may be formed through patterning of a hard mask, forming a lattice mismatch layer, forming a strained silicon layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.

Diffused MOS devices with strained silicon portions and methods for forming same

A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material. In addition, the etch rate of the sacrificial layer should be sufficiently higher than that the ultra thin layer so that the sacrificial layer can be selectively removed in the presence of the ultra thin layer after recrystallization. The latter condition is illustratively satisfied by doping the sacrificial layer and by not (intentionally) doping the ultra thin layer. In accordance with one embodiment of our invention, step (g) includes filling the trench with oxide to form a thick back oxide region. In accordance with another embodiment of our invention, step (g) includes depositing a thin oxide layer (the back oxide) in the trench and then filling the remainder of the trench with a polycrystalline region (the back gate). VRG MOSFETs fabricated in accordance with our invention are expected to be electrostatically scalable with precise dimensional control. In addition, they can be fully depleted. Novel UTB device designs are also described.

Method of making ultra thin body vertical replacement gate MOSFET

A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

CMOS integrated circuit having vertical transistors and a process for fabricating same

Ultra thin body vertical replacement gate MOSFET

The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.

Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor

A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

Process for fabricating vertical transistors

A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.

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Short Hills, NJ, United States of America

John Michael Hergenrother