International Business Machines Corporation

John Michael Hergenrother

Alexander Reznicek

Jeffrey W Sleight

Paul Michael Solomon

Min Yang

Chun-Yung Sung

Victor Chan

Rajesh Rengarajan

Massimo V Fischetti

Meikei Ieong

Anna Wanda Topol

David Michael Fried

Michael Joseph Rooks

Sharee Jane McNab

Shreesh Narasimha

Omer H Dokumaci

Zhibin Ren

Dinkar Virendra Singh

MeiKei Leong

A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a &#x3c;110&#x3e; crystal orientation and a biaxial compressive strain. The term 'biaxial compressive stress' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing &#x3c;110&#x3e; layer; and creating a biaxial strain in the silicon-containing &#x3c;110&#x3e; layer.

Enhancement of electron and hole mobilities in &#x3c;110&#x3e; Si under biaxial compressive strain

Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

Halo-first ultra-thin SOI FET for superior short channel control

A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Method for co-alignment of mixed optical and electron beam lithographic fabrication levels

A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.

Selective incorporation of charge for transistor channels

A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

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Ridgefield, CT, United States of America

John Michael Hergenrother