Motorola Corporation

Other

John Michael Buss

James Douglas Dworkin

Stephen L Smith

Shay-Ping T Wang

Michael J Torla

Scott Edward Lloyd

Robert I Foster

Rodney C Tesch

Shao Wei Pan

ShaoWei Wei Pan

A co-processor ( ) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier ( ) receives sixteen bit data values stored in an A/B RAM ( ) and generates a partial product. The generated partial product is summed in an adder ( ) with a previous partial product stored in a product RAM ( ). A modulo reducer ( ) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM ( ) stores the data value N that is added in a modulo reducer ( ) to the summed value. The co-processor ( ) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method for fast modular multiplication

A programmable versatile digital signal processing system architecture (FIG.,) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG.,) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS.,and,).

Versatile digital signal processing system

A co-processor (,) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (,) receives sixteen bit data values stored in an A/B RAM (,) and generates a partial product. The generated partial product is summed in a summer (,) with a previous partial product stored in a product RAM (,). A modulo reducer (,) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (,) stores the data value N that is added in a modulo reducer (,) to the summed value. The co-processor (,) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method of modulo multiplication

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).

Hybrid instruction set for versatile digital signal processing system

A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Exponentiation circuit utilizing shift means and method of using same

A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable, The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript, The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

Computational array and method for calculating multiple terms of a

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

Logarithm/inverse-logarithm converter utilizing a truncated Taylor

A floor lamp apparatus is provided in which an elongated lightbulb, preferably a fluorescent lightbulb, is supported above the floor. The apparatus is preferably triangular, the first and second sides of the triangle forming a support structure, and the elongated lightbulb being fixed along the third side. The elongated lightbulb can thereby be supported above the surface by either of the first and second sides, and at different angles relative to the surface. The invention is particularly useful to detachably support fluorescent light units of the type having at least one elongated fluorescent lightbulb fixed to an elongated channel housing. a cradle can be formed in the third side to receive and retain the channel housing. Adjacent sides are preferably detachable, or pivotally connected, to permit convenient folding and storage of the apparatus.

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Tempe, AZ, United States of America

John Michael Buss