International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Globalfoundries Inc.

Google Inc.

John Michael Borkenhagen

Gerald Keith Bartley

Philip Raymond Germann

William Paul Hovis

Philip Rogers Hillier, Iii

Darryl John Becker

William Joseph Armstrong

David R Engebretsen

Martin Joseph Crippen

Dhruv Manmohandas Desai

James Anthony Marcella

James Edward Hughes

Steven M Tri

James A O'Connor

Paul Eric Dahlen

William Gavin Holland

Andrew Henry Wottreng

Daniel Paul Kolz

Mark Owen Maxson

William Thomas Flynn

Paul William Rudrud

James David Strom

Richard James Eickemeyer

Christopher W Steffen

Grant Paul Kesselring

Andrew Benson Maki

Brian Thomas Vanderpool

Duane Arlyn Averill

Sheldon Bernard Levenstein

Robert Allen Drehmel

Todd Alan Greenfield

Randolph Scot Kolvick

Eugen Schenfeld

Joseph Allen Kirscht

Pravin S Patel

John David Irish

Sumeet Kochar

Steven R Kunkel

Mark S Fredrickson

Bradley David McCredie

William Hugh Cochran

Ann Chen Wu

Benjamin F Carter, Iii

Stephen Roland Levesque

James Ira Brookhouser

Jack Allan Mandelman

Daniel Mark Dreps

James Stephen Fields, Jr

Bulent Abali

Steven Michael Douskey

Russell Dean Hoover

Moises Cases

Jay Symmes Bryant

David Alan Shedivy

Nam Huu Pham

Shmuel Ben-Yehuda

David John Krolak

Herschel Akiba Ainspan

Robert Russell Williams

Chad M Albertson

Dan Edward Poff

Andrew Douglas Davies

Charles Porter Geer

Herman Lee Blackmon

Sudhir Dhawan

Jan Michael Janick

Anthony Nicholas Liguori

Scott Douglas Frei

David Grant Wheeler

Sandra S Woodward

Quentin G Schmierer

James A Steenburgh

Erik S Unterborn

Gerald G Fagerness

Michael D Day, Ii

Lawrence Dean Whitley

Laura Marie Zumbrunnen

Spencer K Millican

David LeRoy Guertin

Ryan A Harper

Randolph Scott Kolvick

Jerome Martin Meyer

Mark Z Solomon

Philip Rodgers Hillier, Iii

Rashmi Bindu

William G Hollan

James A O'Connoor

Michael A Muston

A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

Phase-locked loop update cancellation

Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.

Dual loop charge pump for enhanced reliability and power consumption

On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.

On-chip spread spectrum synchronization between spread spectrum sources

A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

Phase locked loop pulse truncation

A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.

Higher yielding improved matching reference circuit especially applicable for high speed mixed signal applications and phase locked loops and charge pumps

A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Voltage-controlled oscillator with centertap bias

Techniques for analysis of verification parameters and reduction of training data are provided. A plurality of test results is received, where each of the plurality of test results specifies a respective one or more parameters and a respective one or more events. A list of parameters used to stimulate computing logic is determined. Additionally, a plurality of relevant parameters is generated, corresponding to parameters in the list of parameters that have at least two distinct values specified in the plurality of test results. A plurality of training cases is generated based on the plurality of test results and the plurality of relevant parameters. Further, a neural network is generated for design verification of the computing logic based on the plurality of relevant parameters. The neural network is trained based on the plurality of training cases.

Analysis of verification parameters for training reduction

The invention relates to a method, a circuit, and an apparatus for detecting distortion in spread spectrum signals. An edge in a spread spectrum clock signal is identified based on a reference clock signal. The edge data is then provided to a set of counters which are incremented corresponding to an identified edge. Each bit of a respective output of the counters are provided to a respective OR gate of a set of OR gates. An OR gate from the set of OR gates corresponding to a selected bit then outputs an indication of whether distortion exists in the spread spectrum clock signal.

Detecting distortion in spread spectrum signals

Techniques are disclosed for faster loading of data for hardware accelerators. One technique includes after determining that an accelerator is not ready to perform a workload, identifying data associated with performing the workload and negotiating for the data on behalf of the accelerator. After the negotiation, a cache directory entry associated with the data is marked with a 'claimed' state indicating that the accelerator has obtained ownership of the data but does not have possession of the data. After an indication that the accelerator is ready to accept the data for the workload is received, the data is moved from a previous owner that has possession of the data to the accelerator. Another technique includes requesting a processing unit to perform a workload. If the processing unit is not ready to perform the workload, a translation cache used by the processing unit is warmed up by another unit.

Techniques for faster loading of data for accelerators

Detecting the health of a phase-lock loop (PLL) generating a feedback clock signal based on a reference clock signal, includes providing, by a delay line, the feedback clock signal to a plurality of latches clocked by the reference clock signal; providing, based on an output of the plurality of latches, an input to a plurality of sticky latches, the input indicating whether an edge of the feedback clock signal was detected; determining, based on a number of asserted sticky latches of the plurality of sticky latches, a phase error metric; comparing the phase error metric to a threshold; and outputting, based on the comparison, an indication of a lock state.

Detecting the health of a phase loop lock

Systems and methods to mirror data and otherwise manage memory are provided. A buffer may be coupled to a processor and be configured to write a first copy of data to a first memory located at a first server computer and a second copy of the data to a second memory that is accessible to both the first server computer and a second server computer. The buffer may be coupled directly to at least one of the first memory and the second memory via a memory bus, copper cable, or an optical cable. The buffer may write the first and the second copies of the data concurrently.

Mirroring high performance and high availablity applications across server computers

A system according to one embodiment includes at least two socket servers each having a plurality of sockets, each socket being configured to receive a processor, and a plurality of adapters coupled to the serial computer expansion buses, the adapters being configured to enable communication between the processors of different ones of the socket servers. Each of the socket servers have at least one serial computer expansion bus coupled to each of the sockets thereof.

Multi-server system interconnect

A method includes running a scale-up hypervisor on a server complex including at least one server and running a single operating system and at least one application on top of the scale-up hypervisor. The method further includes identifying a firmware update available for a first hardware component within the server complex. The scale-up hypervisor removes all workload from the first hardware component, and the identified firmware update is applied to the first hardware component while the first hardware component is idle and the hypervisor continues running the single operating system and the at least one application. Preferably, the method may be used to sequentially apply firmware updates to various hardware components across the plurality of servers without ever shutting down the entire plurality of servers.

Applying firmware updates in a system with zero downtime by selectively offlining and onlining hardware using a scale-up hypervisor layer

Hardware component repair in a computing system while workload continues to execute on the computing system includes receiving an indication that an operational parameter of a first hardware resource of said computing system does not meet operational acceptability criteria; migrating workload of the computing system from said first hardware resource to a second hardware resource within the computing system; and halting operation of said first hardware resource for repair.

Repairing a hardware component of a computing system while workload continues to execute on the computing system

Symmetric multi-processor (SMP) nodes are dynamically configured via SMP sockets that use SMP optically-connected switches to dynamically connect SMP optically-connected links connected to the SMP nodes to form SMP domains based on best matched expected workloads for coherent traffic for exchanging SMP coherent information. The SMP nodes are dynamically added to one of the SMP domains and/or dynamically removed from one of the SMP domains.

Dynamic formation of symmetric multi-processor (SMP) domains

Growing community of inventors

Rochester, MN, United States of America

John Michael Borkenhagen