International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

John Matthew Safran

Chandrasekharan Kothandaraman

Byeongju Park

Norman Whitelaw Robson

Deok-Kee Kim

Dan Moy

Mukta G Farooq

Toshiaki Kirihata

Ping-Chuan Wang

Timothy Dooling Sullivan

Fen Chen

Gregory J Fredeman

John A Griesemer

Alan James Leslie

Sami Rosenblatt

Darren Lane Anand

Lijuan Zhang

Chandrasekaran Kothandaraman

Alberto Cestero

Chung-Hsun Lin

Daeik Daniel Kim

Kenneth Jay Stein

Joyce C Liu

Yan Zun Li

Jochonia N Nxumalo

Tak H Ning

Zhong-Xiang He

Douglas Duane Coolbaugh

Herbert Lei Ho

Robert Mark Rassel

Gregory John Uhlmann

Jin Cai

Ebenezer E Eshun

Anthony Gus Aipperspach

Hongwen Yan

Ephrem G Gebreselasie

Yunsheng Song

Gary William Maier

Jean-Oliver Plouchart

Hoki Kim

Raminderpal Singh

Lawrence F Wagner, Jr

Phil Christopher Felice Paone

David Edward Schmitt

Yue Tan

Michael S Cranmer

Yongsang Cho

Daniel Jacob Fainstein

Brian Joy Reed

John William Kay

Mohamed Talbi

Kun Wu

Jon Erik Lieberman

Eileen Veronica Clarke

Daniel Lee Pierce

Robert Joseph Quickle

Christine Ann Kostek

An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Electromigration monitor

A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability

An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface area of the TSV. At least one second interconnect layer disposed over the first interconnect layer includes a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV. The method includes forming a first interconnect layer including a plurality of V0 vias disposed on a TSV, the V0 vias positioned laterally within an upper surface area of the TSV, and forming at least one second interconnect layer disposed over the first interconnect layer and including a plurality of vias laterally positioned outside of a keep out zone positioned over the TSV.

Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects

Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.

Transistor structures gated using a conductor-filled via or trench

A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

Structures and methods for monitoring dielectric reliability with through-silicon vias

A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Through-substrate via shielding

One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking

A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Electrically programmable fuse using anisometric contacts and fabrication method

An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Secure anti-fuse with low voltage programming through localized diffusion heating

An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

Method of programming electrical antifuse

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Wappingers Falls, NY, United States of America

John Matthew Safran