Formfactor, Inc.

Logitech Europe S.a.

John Matthew Long

Charles A Miller

Aron Michael Rosenberg

Nick Stoughton

Jonathan Reckless

Roy John Henson

In some embodiments, a video doorbell system includes a video doorbell device on an exterior surface of a structure and a chime kit within an interior of the structure. A transformer can be coupled in-series via electrical conductors with the video doorbell device and the chime kit. The chime kit can include an energy storage device that is charged via the electrical conductors. When a user activates a button on the video doorbell device power control circuitry within the video doorbell device can transmit a signal on the electrical conductors. Button detection circuitry within the chime kit can detect the signal and respond by transferring power from the energy storage device to a chime. While the chime is activated the transformer can continuously supply the video doorbell device with power.

Doorbell system with energy storage device

In some embodiments, a power supply in a doorbell system includes a boost rectifier circuit with a plurality of active devices arranged in a bridge topology that are configured to receive an AC input voltage, generate a DC output voltage by rectifying the AC input voltage, drive an electric load using the rectified DC voltage, and boost an amplitude of the AC input voltage. Two of the plurality of active devices in the boost rectifier circuit may be pulse driven and can control an operation of a mechanical or digital chime device. The chime device can include a solenoid and the boost rectifier circuit may utilize the solenoid as an energy storage element to facilitate the boosting of the amplitude of the AC input voltage. The boost rectifier circuit may boost the AC input voltage by at least a multiplication factor of two.

Doorbell system with pulse-driven boost rectifier

An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Closed-grid bus architecture for wafer interconnect structure

Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.

System for measuring signal path resistance for an integrated circuit tester interconnect structure

A probe head for testing devices formed on a semiconductor wafer includes a plurality of probe DUT (device under test) arrays. Each device under test includes pads that are urged into pressure contact with probes in a corresponding probe DUT array. The probe arrays patterns have discontinuities such as indentations, protuberances, islands and openings that are opposite at least one device when the probes contact the pads.

Probe head arrays

A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics. Behavior models of the IC and its interconnect systems, based on the behavior models of their selected component, are subjected to simulation and verification tools to determine whether the IC and its interconnect systems meet various performance criteria and constraints. The structural models of the interconnect systems developed during the design process guide subsequent fabrication of interconnect systems for both the IC's intended testing and operating environments.

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San Jose, CA, United States of America

John Matthew Long