Celera Corporation

Cree Microwave, Inc.

Cree Gmbh

Rovec Acquisitions Ltd., LLC

John Mason

Karen Mason

Calum MacRae

Johan Agus Darmawan

Richard Philpott

Jeff A Babcock

Muhammed Abid Hussain

Jim LoCascio

Ly Diep

Jeff Babcock

Some embodiments of the present disclosure include techniques for generating a capacitor comprising receiving a total capacitance for a capacitor to be generated, determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance, generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance, and generating a layout comprising N capacitor layout elements configured to produce said capacitor.

Automated circuit generation

In some embodiments, a computer-implemented method of generating a resistor comprises receiving a first resistor value, converting the resistor value into a plurality of resistor layout segments, and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value.

In some embodiments, information specifying a transistor to be generated is received, the information comprising an on resistance. A total width of a gate of the transistor to be generated is determined based at least on the on resistance. A first width, a number of fingers (F), and a number of device cells (P) are determined based on the total width. A transistor level schematic is generated comprising one or more transistors configured with the first width and the number of fingers (F). A layout is generated, wherein the layout comprises P device cells, each device cell comprising a plurality of gates corresponding to said number of fingers (F) each gate having said first width, wherein the device cells are configured in a two-dimensional array.

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Automated circuit and layout generation is disclosed. Various embodiments may include a computer system and/or method for generating a circuit layout comprising specifying a circuit schematic to be converted to a circuit layout, receiving a layout script associated with the circuit schematic, the layout script configured to position a plurality of layout instances generated from the circuit schematic, converting the circuit schematic into the plurality of layout instances; and positioning the plurality of layout instances based on the layout script to produce the circuit layout. A circuit may be produced by fabricating a circuit using the layout.

Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.

Laterally diffused MOS transistor having N+ source contact to N-doped substrate

A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.

LDMOS transistor with improved gate shield

An improved laterally diffused MOS (LDMOS) transistor architecture is provided by using a nitride cap on a gate structure and forming a spacer around the gate structure and then self-aligning a source contact and drain contact with a gate by using the same mask for source and drain dopant implantation and for silicide formation with all source and drain areas being silicided. The reduced source/drain on resistance (Rdson), shorter distance from channel to source contact, and better gate oxide integrity improves operating linearity, increases Ft and GM and reduces the drift in Idq and Rdson.

Growing community of inventors

Sunnyvale, CA, United States of America

John Mason