International Business Machines Corporation

John Martin Ludden

Allon Adir

David A Campbell

Bryan Glen Hickerson

Charles Meissner

Bradly George Frey

Jentje Leenstra

Guerney D H Hunt

Avi Ziv

David Andrew Schroter

Benjamin Herrenschmidt

George W Rohrbaugh, Iii

Paul Mackerras

Gil Eliezer Shurek

Olaf Knute Hendrickson

Madhusudan Kadiyala

Brad Lee Herold

Lance G Hehenberger

Pedro Martin-de-Nicolas

Elena Tsanko

Darin Marcus Greene

Wallace Sharp

Jeremy John Salsman

Brenton Yiu

Anatoli Andreev

Richard D Peterson

Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.

Functional test of processor code modification operations

The present disclosure relates to a process-based virtualization system comprising a data processing unit. The system comprises a computer readable storage media, wherein a first memory component of the computer readable storage media is configured for access by an OS, secure and non-secure applications and the firmware, and wherein a second memory component of the computer readable storage media is configured for access by the firmware and not by the OS and the non-secure application. The data processing unit is configured to operate in a first mode of operation that executes a non-secure application process using the OS, and to operate in a second mode of operation that executes the secure application using the firmware, thereby executing application code using the second memory component.

Process-based virtualization system for executing a secure application process

Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.

Methods and systems for verifying out-of-order page fault detection

An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Verifying correctness of processor transactions

A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path. The re-direction instructions may be illegal instructions, which cause execution of an interrupt handler that performs the replacement.

Two pass test case generation using self-modifying instruction replacement

Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.

Efficient and self-balancing verification of multi-threaded microprocessors

A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Software table walk during test verification of a simulated densely threaded network on a chip

A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are received for a set of constraints for generating test simulation vectors for branch conditional instructions. Current resource values for predicting a branch for a branch conditional instruction are read. A branch operand field is generated to include a set of valid values using the current resource values and based upon said user selected constraints. The branch operand field defines conditions under which a branch is taken.

Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors

A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique and/or processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. A high-level program controlling simulation of a VHDL model of a processor can simulate extension of the completion time of a predetermined instruction in order to hold the instruction in the execution and completion queues, placing an effective hold on the resources allocated for the instruction. Alternatively, the VHDL model may include logic for controlling completion timing of the program instruction by using a processor clock cycle counter. Verification testing of actual processor hardware may be facilitated by including the counter and associated control logic within production or prototype processors.

Method and apparatus for controlling program instruction completion timing for processor verification

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Essex Junction, VT, United States of America

John Martin Ludden