Credence Systems Corporation

John Mark Oonk

Brian J Arkin

Laurence Crosby

A method for determining an output voltage of a device under test is disclosed. In the method, a first voltage is placed onto a terminal of a resister that is coupled to the device under test and a first current is through the resistor that corresponds to the first voltage is measured. A second voltage is then placed onto the terminal of the resistor and a second current is measured through the resistor that corresponds to the second voltage. An actual resistance of the resistor is computed based on the difference between the first voltage and the second voltage divided by the difference between the first current and the second current. An output voltage of the device under test is calculated based on a magnitude of a measured current through the resistor when the terminal is grounded multiplied by a magnitude of the actual resistance of the resistor.

Method and device for enabling the measurement of device under test voltages using a testing instrument of limited range

A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a 'fail' bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also includes a set of programmable area fail counters, each for counting of the number of memory cells within a separately selected area of the memory's address space. After the test, the computer processes the counts to determine whether it needs to allocate the spare rows and columns and, in some cases, to determine how to allocate the spare rows and columns. When it cannot allocate spare rows and columns on the basis of the counts alone, the computer commands the tester to read the fail bits in selected areas of the ECM's address space to determine the addresses of the defective memory cells and to supply those addresses to the computer to enable it to determine how to allocate spare rows and columns.

Apparatus for testing memories with redundant storage elements

An integrated circuit (IC) tester employs a pattern generator including an instruction processor executing an algorithmic program stored in a program memory. The program defines a sequence of vectors defining test activities to be carried out during successive cycles of a test on an IC. In the course of executing the program, the instruction processor stores in various registers and counters &ldquo;program status&rdquo; data that the processor uses to keep track of program execution. The status data may include, for example, the current program memory address, loop and repeat counts, return addresses and the like. The pattern generator also includes a random access &ldquo;program status&rdquo; memory for storing a selected portion of the program status data at selected points during a test. The algorithmic program defining the vectors to be produced for each cycle of the test also selects a test event (such as a DUT failure) that is to trigger program status data storage during any test cycle, selects the particular status data to be stored in response to the test event, and selects the status memory address at which the data is to be stored. Test analysis software may read the program status data out of the program status memory following the test and use it to determine the status of program execution at the time the triggering events occurred.

Integrated circuit tester having a program status memory

An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.

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San Ramon, CA, United States of America

John Mark Oonk