International Business Machines Corporation

John Mark Kaczmarczyk

Agnes Yee Ngai

Charles E Boice

Barbara A Hall

Michael Patrick Vachon

James David Greenfield

Robert L Woodard

Adrian Stephen Butter

Edward Francis Westermann

Robert J Yagley

Stephen Philip Pokrinchak

Lilla Boroczky

Lawrence D Curley

Charles John Stein

John A Murdock

Charlene Ann Gebler

Robert Leslie Woodward

A digital video encoder is presented adapted for dynamically switching between sets of quantizer matrix tables without pausing encoding of a stream of video data. Two or more sets of quantizer matrix tables are held at the encoder's quantization unit and compressed store interface for dynamically switching between sets of quant matrix tables at a picture boundary of the sequence of video data, i.e., without stopping encoding of the sequence of video data. Further, while one set of matrix tables is being employed to quantize the stream of video data, the encoder can be updating or modifying another set of quantization matrix tables, again without stopping encoding of the sequence of video data.

Dynamically switching quant matrix tables within an MPEG-2 encoder

Method and encoder for encoding a digital video image stream. The encoding includes spatial compression of still images in the video stream and temporal compression between the still images. The spatial compression is carried out by converting a time domain image of a macroblock to a frequency domain image of the macroblock, taking the discrete cosine transform of the frequency domain image, transforming the discrete cosine transformed macroblock image by a quantization factor, and run length encoding the quantized discrete cosine transformed macroblock image. The temporal compression is carried out by reconstructing the run length encoded, quantized, discrete cosine transformed image of the macroblock, searching for a best match macroblock, and constructing a motion vector between them. This forms a bitstream of run length encoded, quantized, discrete cosine transform macroblocks and of motion vectors. This bitstream is passed to and through an external buffer to a transmission medium. The number encoded bits read by a host from the external buffer is fed back to the encoder for calculation in real time of a dynamic buffer level indicator indicative of the fullness of the external buffer. The encoder may generate a BUFFEREMPTY flag, BUFFERALMOSTFULL flag and/or BUFFERFULL flag for the host.

On-chip dynamic buffer level indicators for digital video encoder

Temporal compression of a digital video data stream with hierarchically searching in at least one search unit for pixels in a reference picture to find a best match for the current macroblock. This is followed by constructing a motion vector between the current macroblock and the best match macroblock in the reference picture.

Efficient, flexible motion estimation architecture for real time MPEG2 compliant encoding

System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

Apparatus and method for power reduction control in a video encoder device

A digital video encoder system having a motion estimation processor, and an interface to the motion estimation processor. The motion estimation processor includes a reference memory interface, and inverse quantization processor, an inverse discrete cosine transform processor, and a motion estimation processor unit including a hierarchal search unit. The motion estimation processor is utilized generating temporally compressed datastreams, that is, I-P and I-P-B datastreams.

Motion estimation processor for a digital video encoder

More than 2 power N external conditions are determined by a circuit package. Connections are made from N inputs to either a first or second contact at either a first or second logic state respectively or to digital outputs. The outputs may be sequentially placed at either the first or second logic state. By recording an indication signal from the inputs an electronic circuit is adapted to determine more than 2 power N conditions.

Circuit and method for differentiating multiple modules

Method, system and computer program product are provided for adaptively encoding in hardware, software or a combination thereof a sequence of video frames in real-time. A first encoding subsystem is employed to analyze the sequence of video frames to derive information on at least one characteristic thereof, such as motion statistics, non-motion statistics, scene change statistics, or scene fade statistics. The gathered information may comprise either an intraframe characteristic or an interframe characteristic. A second encoding subsystem, coupled to the first encoding subsystem, encodes the sequence of video frames employing at least one controllable parameter. The second encoding subsystem dynamically adapts intraframe or interframe encoding of the sequence of video frames by adjusting the at least one controllable parameter used in the encoding process in response to the derived information from the first encoding subsystem.

Adaptive real-time encoding of video sequence employing image statistics

A method to compensate for a fade in a digital video input sequence is provided where the video input sequence is to be compressed according to the MPEG-2 video compression standard. The method comprises a first step of dividing each frame of a current frame into two fields. In a second step, each field of the current frame is divided into at least one field band. In a third step, the luminance and chrominance pixel values are individually summed for the pixels in each field of the current frame. In a fourth step, the luminance pixel values are summed for the pixels in each field band of the current frame. In a fifth step, each respective field band sum and field sum of the current frame is compared with that of the previous frame in the video input sequence. In a sixth step, detection of whether or not a fade has occurred is provided, based upon the comparison in the fifth step. In a seventh step, the encoding algorithm is adjusted if a fade has occurred. Lastly, the first through seventh steps are repeated for at least one subsequent frame in the input video sequence.

Method to compensate for a fade in a digital video input sequence

Method, system and computer program product are provided for adaptively encoding in hardware, software or a combination thereof a sequence of video frames in real-time. A first encoding subsystem analyzes the sequence of video frames to derive information on at least one characteristic thereof, such as motion statistics, non-motion statistics, scene change statistics, or scene fade statistics. The gathered information may be either an intraframe characteristic or an interframe characteristic. A control processor is coupled to the first encoding subsystem to automatically analyze the gathered information in real time and dynamically produce a set of control parameters. A second encoding subsystem, coupled to the control processor, then encodes each frame of the sequence of video frames employing the corresponding set of control parameters.

Real-time encoding of video sequence employing two encoders and

A method for spatial compression of a digital video picture to obtain the quantizer step size so as to avoid over 'lossy' reconstruction and loss of detail. The first step is dividing the picture into a plurality of macroblocks, for example, 16.times.16 macroblocks, each macroblock having luminance or chrominance pixel blocks, for example four 8.times.8 pixel blocks. This is followed by multiplying each luminance pixel block by a modified frequency ordered Hadamard matrix to yield a first dimension of each luminance pixel block. The first dimension of each pixel block is then multiplied by the inverse of the modified frequency ordered Hadamard matrix to yield a second dimension of each luminance pixel block. The second dimension of the pixel luminance block is then weighted against a weight matrix, and the individual weighted terms are summed for each pixel block. The minimum of the weighted terms is selected. This minimum is used to detect the edge or texture of the macroblock, e.g., for setting the quantizer step size.

Method for adaptive quantization by multiplication of luminance pixel

A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

Scalable MPEG2 compliant video encoder

Method and apparatus for encoding a digital video image stream in an encoder. The encoding includes spatial compression of still images in the digital video image stream and temporal compression between the still images. The spatial compression is carried out by converting a time domain image of a macroblock to a frequency domain image of the macroblock, taking the discrete cosine transform of the frequency domain image, transforming the discrete cosine transformed macroblock image by a quantization factor, and run length encoding the quantized discrete cosine transformed macroblock image. The temporal compression is carried out by reconstructing the run length encoded, quantized, discrete cosine transformed image of the macroblock, searching for a best match macroblock, and constructing a motion vector between them. This forms a bitstream of runlength encoded, quantized, discrete cosine transformed macroblocks and of motion vectors. This bitstream is passed to and through a FIFO buffer to a transmission medium. The number of run length encoded bits is fed back to the encoder for calculation of the quantization factor, to thereby avoid overrunning the buffer and interrupting the transmission.

FIFO feedback and control for digital video encoder

Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths. The datapaths are partitionable by the action of running opcode into (i) a single wide datapath, and (ii) a plurality of narrow datapaths for calculating the absolute value of the difference between two pixels, and accumulating the results of the subtraction.

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Endicott, NY, United States of America

John Mark Kaczmarczyk