Hewlett-Packard Company

John Manton

Michael Kahaiyan

Daryl Francis Kinney

Barry J Flahive

Richard G Bahr

Stephen J Ciavaglia

John S Yates, Jr

Anthony N Drogaris

Christopher H Mills

Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor. Pending instructions are subsequently re-executed in the sequence of their occurrence at the time the exception provoking instruction caused the processor to inhibit further instruction execution. Completed instructions are not re-executed. Applicable to computing systems having a plurality of processors, of either the same or different type such as floating point and integer processors, the method and apparatus inhibits all such further execution of plural processors upon the detection of an exception in one of the processors. In processors other than the processors serving the exception, no-op instructions are executed until the processor servicing the exception causes pending instructions to be re-executed, at which time the other processors also re-execute instructions which were pending at the time further execution of the instructions was inhibited.

Method and apparatus for exception handling in pipeline processors

Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units, to provide the execution efficiency of systems with a single instruction length.

Data processing system for concurrent dispatch of instructions to

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Marlboro, MA, United States of America

John Manton