Intel Corporation

John Mangan

Niall D McDonnell

Bruce Richardson

Francesc Guim Bernat

Kshitij Arun Doshi

John Joseph Browne

Susanne M Balle

David Sonnier

Mark D Yarvis

Mats Gustav Agerstam

Stephen T Palermo

Marcos Emanuel Carranza

Edwin Verplanke

William G Burroughs

Rahul R Shah

Shrikant M Shah

Thijs Metsch

Chetan Hiremath

Bin Li

Benjamin Walker

Dario Oliver

Abhishek Khade

Adrian C Hoban

Mrittika Ganguli

Gage Eads

Mikko Ylinen

Brian A Keating

Abhirupa Layek

Ciara Loftus

Sarita Maini

Bradley Chaddick

David Cremins

Niall Mcdonnell

Harry Van Haaren

Praveen Mosur

Various systems and methods for implementing intent-based cluster administration are described herein. An orchestrator system includes: a processor; and memory to store instructions, which when executed by the processor, cause the orchestrator system to: receive, at the orchestrator system, an administrative intent-based service level objective (SLO) for an infrastructure configuration of an infrastructure; map the administrative intent-based SLO to a set of imperative policies; deploy the set of imperative policies to the infrastructure; monitor performance of the infrastructure; detect non-compliance with the set of imperative policies; and modify the administrative intent-based SLO to generate a revised set of imperative policies that cause the performance of the infrastructure to be compliant with the revised set of imperative policies.

Intent-based cluster administration

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

Virtual switch scaling for networking applications

Growing community of inventors

Shannon, Ireland

John Mangan