Intel Corporation

John Maddux

Jonathan H Liu

Joseph H Salmon

Luke A Johnson

Alexander Levin

Ronald W Swartz

Michael W Altmann

Rajashri Doddamani

Hing “Thomas” Y To

Surya N Koneru

Donald Rush

Hing &ldquo;Thomas&rdquo; Y To

Meetul Goyal

Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.

Methods and systems to calibrate push-pull drivers

A system and method for training a clock signal are described. The method includes determining a first position of a clock signal by training the clock signal using a first test data, determining a final position of a clock signal by training the clock signal using a second test data, and using the offset between these positions to speed up subsequent trainings.

System and method for alignment of clock to data

A circuit comprising a sampling logic to sample an incoming signal. A phase detection logic to determine a phase error associated with the sample of the incoming signal and to output an out-of-phase detection signal based on the phase error. A control logic coupled to the phase detection logic to output a periodic error signal at a periodic rate. A phase adjustment logic to adjust the phase of the sampling logic based on the out-of-phase detection signal and the periodic error signal.

Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit

A method to calibrate I/O cell current has been described. The method includes setting a global control value provided to the I/O cells. Then, for each I/O cell, the method includes comparing the logic voltage at the output pad of the I/O cell with a reference voltage, and sinking more current at the output pad by enabling additional driver bits associated with the I/O cell if the logic voltage is higher than the reference voltage, or sinking less current at the output pad by disabling additional driver bits associated with the I/O cell if the logic voltage is lower than the reference voltage.

Dynamic current calibrated driver circuit

An apparatus and a method to control an output signal from a DAC-driven amplifier-based driver are disclosed. The apparatus includes an amplifier and a driver. The amplifier has a negative input terminal, a positive input terminal, and a first output terminal. The driver has an input terminal and a second output terminal, the input terminal coupled to the first output terminal of the amplifier and the second output terminal coupled to the positive input terminal of the amplifier to provide a positive feedback to the amplifier. In another embodiment, the apparatus includes a first driver to drive an output signal, the first driver having a first input terminal and a first output terminal, a second driver to generate a feedback, the second driver having a second input terminal and a second output terminal, and an amplifier having a third input terminal to receive an input signal, a fourth input terminal, and a third output terminal, the third output terminal coupled to the first input terminal of the first driver and the second input terminal of the second driver, the fourth input terminal coupled to the second output terminal of the second driver.

Output signal control from a DAC-driven amplifier-based driver

A local driver circuit to drive a logic voltage at an output pad includes an adder having K bits to add a K-bit control value to a local value, the adder producing a K-bit calibrated value. The circuit further includes K field-effect transistors (FETs), the drain of each FET being coupled to the output pad, and logic circuitry to perform a logical-AND function between a data input and the K-bit calibrated value. The logic circuitry providing a K-bit output with each of the K output bits being coupled to the gate of a corresponding one of the FETs. A comparator produces a correction value from a comparison of the logic voltage at the output pad and a reference voltage. A control unit sets a least significant bit (LSB) portion of the local value responsive to the correction value so as to make the logic voltage at the output pad in the reference voltage substantially equal.

An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.

Generating a clock signal

In general, one embodiment of the invention involves an apparatus that comprises a fast acquisition logic coupled to an oversampler. The fast acquisition logic is configured to detect whether any of a plurality of data samples produced by the oversampler is inaccurate, and if so, to cause data to be recovered from a new data sample different from the data sample previously being used for data recovery. The new data sample would be multiple sampling states away from the previous data sample.

Apparatus and method for acquisition of an incoming data stream

A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.

Testing IO timing in a delay locked system using separate transmit and receive loops

A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.

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Folsom, CA, United States of America

John Maddux