Standard Microsystems Corporation

John M Zapisek

Gus Giulekas

John F Tweedy, Jr

A programmable logic array includes a plurality of MOS switching devices formed at preselected locations in an array made up of input and output lines and intersecting product term lines. One group of MOS devices constituting the 'AND' plane arranged at the intersections of the input lines and product term lines performs a logic operation on input signals to the array and outputs logic signals onto the product term lines. A second group of MOS devices constituting the 'OR' plane located at the intersections of the output lines and product term lines receives the outputs of the 'AND' plane devices and performs a logic operation on those signals to produce a set of output signals that are presented at the outputs of the array for use by an external device. The merged plane array of the invention advantageously includes dual-gate MOS devices as switching elements to reduce the capacitance on the product term lines and output lines and thereby to increase the operating speed of the array. The input and output lines and related MOS devices of the array rather than being arranged in physically separate and distant input 'AND' and output 'OR' planes, as in the prior art, are interspersed or merged with one another so as to reduce the amount of interconnect required between the logic array and an external device which provides the inputs to the array and receives the outputs therefrom.

High-speed merged plane logic function array

A data separator for providing data and clock information derived from a floppy disk to a controller includes a synthetic oscillator phase-locked loop which adjusts the phase of the derived clock, thereby to tend to position data inputs within the central portion of their associated half-bit slots. The center frequency of the synthetic oscillator may be modified in accordance with prior phase adjustments to compensate for variations in the speed of the floppy disk drive.

Data separator

An internal bias generator for providing a negative bias voltage to the substrate of an MOS integrated circuit at a magnitude higher than the power supply voltage includes a pump circuit which comprises a plurality of switches which are sequentially actuated by nonoverlapping clock signals to alternately charge and discharge a capacitor. The clock signals are produced by a generator which includes a series of RC-delay inverting amplifier stages coupled to a series of NOR gates. The bias generator further comprises a threshold-sensitive regulator which uses the source-body effect of substrate bias on the threshold voltage of an MOS FET to control the magnitude of the applied bias voltage. When the sensed threshold voltage deviates from a desired level, certain of the clock signals are disabled, thereby to modify the bias voltage applied to the substrate in a manner to tend to restore the threshold voltage to its desired level.

Three-phase regulated high-voltage charge pump

A programmable logic array includes a plurality of MOS switching devices formed at preselected locations in an array made up of input and output lines and intersecting product term lines. One group of MOS devices constituting the 'AND' plane arranged at the intersections of the input lines and product term lines performs a logic operation on input signals to the array and outputs logic signals onto the product term lines. A second group of MOS devices constituting the 'OR' plane located at the intersections of the output lines and product term lines receives the outputs of the 'AND' plane devices and performs a logic operation on those signals to produce a set of output signals that are presented at the outputs of the array for use by an external device. The merged plane array of the invention advantageously includes dual-gate MOS devices as switching elements to reduce the capacitance on the product term lines and output lines and thereby to increase the operating speed of the array. The input and output lines and related MOS devices of the array rather than being arranged in physically separate and distinct input 'AND' and output 'OR' planes, as in the prior art, are interspersed or merged with one another so as to reduce the amount of interconnect required between the logic array and an external device which provides the inputs to the array and receives the outputs therefrom.

Growing community of inventors

Hauppauge, NY, United States of America

John M Zapisek