Sri International

Signetics

Koninklijke Philips Corporation N.v.

Nxp B.v.

Velcon Filters, Inc.

John M Yarborough, Jr

Charles S Weaver

Donald J Burch

Joseph H Chadwick

Lucian W Taylor

Floyd A Brown

An R-C oscillator () is configured to vary the two voltage levels that are used to control the oscillation, such that the variation in oscillation frequency with temperature is minimized. A first resistor (R) is used to control one of the voltage levels, and a second resistor (R) having a temperature coefficient that differs from the temperature coefficient of the first transistor is used to control the other voltage level. The first resistor (R) also controls the current used to charge and discharge the capacitor (C) used to effect the oscillation. By the appropriate choice of resistance values, the variations of the control voltages and current are such that the time to charge and discharge the capacitor (C) between the control voltages remains substantially constant with temperature. Preferably the resistance values are selected to also compensate for temperature variations in the delay of the feedback loop.

Temperature compensated R-C oscillator

A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of both an integer divisor as well as a fraction component. The average frequency of the output signal from the fractional divider is dependent upon both the integer divisor and the fraction component, thereby providing for a finer resolution to the average frequency of the output signal. This combination of integer and fractional frequency division is particularly well suited for the generation of signals for systems that are substantially jitter-insensitive.

Baud rate generator with fractional divider

A frequency detector receiving two input frequencies and generating a pump-up/pump-down signal for control of a phase locked loop by matching the frequency of a voltage controlled oscillator to the frequency. The lock is independent of the phase relationship of the signals.

Frequency detector for use with phase locked loop

A phase detector for use with a phase locked loop where the input has missing pulses. The detector processes two input frequencies and generates either a pump-up or a pump-down signal on separate outputs. The reference input may have missing transitions, as often happens in recovering the clock from encoded data. The phase detector comprises three bistable flip-flops and a gate interconnected to respond to the two input frequencies to produce either a pump-up pulse of variable width proportional to the phase difference between the pulses of the two input frequencies or a fixed width pump-down pulse.

Phase detector insensitive to missing pulses

A phase-lock loop is disclosed for synchronizing an oscillator signal with a train of input signal pulses, some of which may be missing. The phase-lock loop is of particular use in a decoder for decoding digitally encoded data employing a self-clocking coding scheme. The decoder generates a clock from the input signal stream for use in the decoding process.

Phase-lock loop and Miller decoder employing the same

A digital decoder for Miller encoded signals is disclosed comprising a resettable counter which is clocked at a frequency which is a large multiple of the base frequency of the Miller encoded signal. Transitions in the Miller encoded data stream are used to reset the counter. Digital signal storage means are provided for storing a digital signal having a value substantially equal to the value to which the counter is advanced in one Miller unit of time. Output logic circuit means responsive to outputs from the counter and digital signal storage means produces a binary output signal indicative of the decoded Miller encoded input signal. Means are provided for recurrently updating the contents of the digital signal storage means to adjust for variations in the base frequency of the Miller encoded input signal.

Digital Miller decoder

Method and apparatus for transferring digital data in a bit stream consisting of digital data words each of which words includes data bits and a parity bit are disclosed. Except for the word parity bits, the stream is transferred without additional overhead bits such as start and stop bits employed in an asynchronous transmission data format or synchronizing characters employed in a synchronous transmission data format. Method and apparatus for locking onto the parity bit of such a bit stream are disclosed which allow for digital data transfer in this format.

Digital data transmission with parity bit word lock-on

A plural channel playback system comprising magnetic recording tape movable past a reproducing transducer head having at least one transducing element for each track is shown together with skew detecting means. At least two of the tracks are recorded with digital data signals comprising equal length data words with a parity bit, with the parity bits being simultaneously recorded along the tracks. Parity bit lock-on circuits are responsive to outputs from two tracks, which lock-on circuits generate word clock pulses in synchronization with the recorded parity bit signals. A phase detector responsive to word clock pulses from the parity bit lock-on circuits produces an error signal output proportional to the phase difference between said word clock pulse inputs thereto, which error signal is related to skew. The azimuthal position of the reproducing head relative to the recording tape is adjusted either manually or automatically to minimize the error signal.

Skew sensing for digital tape playback

Method and apparatus for locking onto the parity bit of a bit stream of equal length words, each of which words includes a parity bit, are disclosed. The bit stream is shifted through a data shift register which includes a plurality of word length sections. Parity of bits contained in the first section of the data shift register is checked every bit interval of the bit stream. Two parity bit shift registers are provided, the first of which is one word in the length and the second of which is of the same length as the data shift register. The output from the parity checking means is connected to serial inputs of said first and second parity bit shift registers through a logic gate controlled by the serial output from the first parity bit shift register. When the serial output from the first parity bit shift register is a 'one' bit, the results of the parity check are entered into said first and second parity bit shift registers through said logic gate, and when the serial output therefrom is a 'zero' bit, a 'zero' bit is entered into said first and second parity bit shift registers. Means are provided for connecting parallel outputs of said second parity bit shift register to a decision logic circuit having a word clock pulse output which is synchronized with parity bits in the bit stream when the apparatus is locked onto parity bits in the stream.

Parity bit lock-on method and apparatus

An averaging circuit for producing average boat speed and average apparent wind speed which in cooperation with average apparent wind direction are utilized to determine the performance characteristics of sailing boats. Instantaneous values of the speed parameters are sampled at a predetermined frequency and a running average of N samples is generated by adding the most recent sample and discarding the oldest sample at periodic intervals. Display of the wind speed is delayed with respect to the display of boat speed to compensate for the effect of the inertia of the boat.

Growing community of inventors

Palo Alto, CA, United States of America

John M Yarborough, Jr