Analog Devices,inc.

John M Wynne

Eamon Hynes

John O'Dowd

William Hunt

John R Martin

Michael C Coln

Damien Joseph McCartney

Oliver J Kierse

Michael Byrne

Albert C O'Grady

Donal P Geraghty

Patrick G Crowley

Peter G Meehan

In various embodiments, a low-cost Rogowski coil sensor including a coil wound around a flexible carrier is provided with a reliable parallel-entry closure mechanism.

Low-cost Rogowski coil sensors

An embodiment of a voltage-measuring circuit includes: a first resistor connected to a first measurement node; a second resistor connected to the first resistor and a second measurement node; a configuration switch configured to, in response to a control signal, selectively interconnect the first and second resistors, during enable and disable phases of the control signal respectively, into and out of either a parallel or a series configuration; and a control and measurement circuit configured to provide the control signal, receive a first measurement voltage from the first and second measurement nodes during the enable phase, and receive a second measurement voltage from the first and second measurement nodes during the disable phase.

Voltage-measuring circuit and method

A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.

Spaced, bumped component structure

A galvanically isolated charge balance system for a multicell battery includes a balancing circuit associated with each cell; each balancing circuit including a flying capacitor; a variable conductance switch; and a biasing circuit for the variable conductance switch; and a galvanically isolating MEMS switching device for selectively connecting the flying capacitor to a voltage supply to charge it to a predetermined voltage and to the biasing circuit for setting the variable conductance switch to adjust the charge on its associated cell to a preselected level.

Galvanically isolated charge balance system

A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Capacitive sensor

A galvanically isolated signal conditioning system includes a signal conditioning circuit on an integrated circuit chip; a flying capacitor; and a galvanically isolating MEMS switching device on an integrated circuit chip for selectively switching the flying capacitor from across a pair of input terminals in one state to across the input terminals of the signal conditioning circuit in another state.

Galvanically isolated signal conditioning system

A multi-channel circuit () comprising a plurality of on-chip channels (CHto CH), each of which comprises a DAC () for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (). The analogue output signals from the DACs () are outputted on output terminals () of the respective channels (CHto CH). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs () are inputted to the interface and control logic circuit () through an I/O port (). DAC registers () are provided in the respective channels (CHto CH) for storing the digital words to be converted in the corresponding DACs (). Analogue input terminals () are provided for receiving analogue input signals (), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (). A multiplexer () is operable under the control of the interface and control logic circuit () for selectively and sequentially applying the analogue output signals from the DACs () and the analogue input signals from the analogue input terminals () to a monitoring output terminal () for facilitating independent monitoring of the analogue output signals from the DACs (), and the analogue inputs on the analogue input terminals ().

Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs

Electro-mechanical structures and methods for forming same are disclosed. The structures are integratable onto an integrated circuit. The structures have a deformeable element formed in a plane substantially perpendicular to the substrate of the integrated circuit.

Integratable transducer structure

An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Method of invoking a power-down mode on an integrated circuit by

An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.

Serial data interface apparatus and method for detecting an input word

A digitally controlled calibration circuit for a DAC includes a primary DAC having a first reference current input, a second input for receiving a digital signal representative of the DAC conversion factor, and an output for providing the analog signal; a secondary calibration DAC has associated with it a reference network connected to a first input of the secondary DAC for conducting a reference current, and a device for connecting the output of the secondary DAC to the reference network, the second DAC includes a second input for receiving a digital signal for adjusting the output of the secondary DAC fed back to the reference network for adjusting the reference current; and a device for interconnecting the reference current with the first reference current input of the primary DAC for digitally controlling the reference current input of the primary DAC for digitally controlling the reference current to that primary DAC and digitally effecting calibration of the primary DAC.

Digitally controlled calibration circuit for a DAC

A low distortion CMOS switch system includes a plurality of N-channel and a plurality of P-channel transistors with their drain and source terminals connected in parallel for receiving an input signal to be switched; and a control circuit for providing a different positive drive voltage to the gate of each of the N-channel transistors and a different negative drive voltage to the gate of each of the P-channel transistors to produce substantially constant 'on' resistance, R.sub.ON, throughout the range of the switched signal conducted through the drain and source terminals, and for providing the same negative drive voltage to the gate of each of the N channel transistors and the same positive drive voltage to the gate of each of the P channel transistors to turn off the transistors.

Low distortion CMOS switch system

A converter for producing the function V.sub.out =V.sub.bias =V.sub.swing (1-2D), in which a DAC is combined with an operational amplifier and (typically) three or four resistors. A function of the voltage V.sub.swing, or a current corresponding thereto, is applied to the reference voltage input terminal of the DAC. The variable D is the DAC's digital input code, expressed as a decimal or fraction in the range between 0 and 1. The DAC output provides a suitably scaled and signed signal which is added to or subtracted from the offset signal V.sub.bias to produce V.sub.out.

Single-supply digital-to-analog converter for control function generation

A four-quadrant multiplier uses a CMOS digital-to-analog converter (DAC) and just one operational amplifier. The back gates of the CMOS switches in the DAC are biased in the 'off' condition during a substantial voltage swing at the output of the DAC. In one embodiment, the back gates of the CMOS switches are held at about -5 V with respect to the output lines, and the logic low level to the off switch also is set at -5 V relative to the output lines. The DAC connections are 'reversed' so as to receive the analog input across the terminals intended as the DAC's output, with the inputs of the operational amplifier being connected across the reference voltage terminal and a feedback or output terminal of the DAC.

Growing community of inventors

Dooradoyle, Ireland

John M Wynne