Rambus Inc.

Nvidia Corporation

North Carolina State University

Seagull Technology, Inc.

John M Wilson

Lei Luo

John Cronan Eble, Iii

Brian S Leibowitz

Wayne D Dettloff

Jared L Zerbe

John Wood Poulton

Barry William Daly

Frederick Abbott Ware

Jade M Kizer

Jihong Ren

Teva J Stone

Sudhir Shrikantha Kudva

Hsuan-Jung Su

James Michael O'Connor

Donghyuk Lee

Michael D Bucher

Huy M Nguyen

Amir Amirkhany

Kyung Suk Oh

Kambiz Kaviani

Chaofeng Huang

Paul Damian Franzon

Walker Joseph Turner

Hsuan-Jung (Bruce) Su

Aliazam Abbasfar

Stephen G Tell

Stephen E Mick

Sanquan Song

Carl Thomas Gray

Matthew Rudolph Fojtik

Joong-Ho Kim

Ian P Shaeffer

Carl William Werner

Nikola Nedovic

David A Secker

Ravindranath T Kollipara

Pravin Kumar Venkatesan

Sunil Rao Sudhakaran

Xi Chen

Yaping Zhou

Anshuman Bhuyan

WooPoung Kim

Yoshinori Nishi

The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

Signaling over RC-dominated transmission lines

Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.

Low-power dynamic offset calibration of an error amplifier

A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.

Interconnection structures to improve signal integrity within stacked dies

Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O

High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

Switched low-dropout voltage regulator

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented 'fast turn-on' bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Method and apparatus for source-synchronous signaling

Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Self-clocking sampler with reduced metastability

An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.

Bus-invert coding with restricted hamming distance for multi-byte interfaces

Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.

424 encoding schemes to reduce coupling and power noise on PAM-4 data buses

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

Unrelaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses

A system comprising a PAM-4 transmitter coupled data lanes includes a least significant bit section and a most significant bit section for the symbols generated on each lane. A controller to determine a state of the PAM-4 transmitter and selectively inverts a polarity of the symbol bits on the lanes based on the state.

Bus-invert coding with restricted weight range for multi-level signaling

Growing community of inventors

Santa Clara, CA, United States of America

John M Wilson