International Business Machines Corporation

Globalfoundries Inc.

John M Sutton

Agnes Yee Ngai

Eric Eugene Retter

Barbara A Hall

Edward Francis Westermann

James David Greenfield

Patrick S Spinney

Donald R Letourneau

Leah J Bagley

The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure includes: bond pads in an active region of a chip; test pad structures in a kerf region of the chip; and hardmask material in the kerf region between the test pad structures and the bond pads. The surfaces of the test pad structures and the bond pads are devoid of the hardmask material.

Wiring bond pad structures

Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.

Real time clock circuit having an internal clock generator

The present invention provides hardware-based synchronization within a device such as a set top box so that sets of data values can be communicated between a set of DCR registers operating at a first frequency and a set of clock register operating at a second frequency. Specifically, to communicate an initial set of data values from the set of DCR registers to the set of clock registers, a control signal is stretched and then synchronized with a clock signal having the second frequency. To communicate a current set of data values from the set of clock registers to the set of DCR registers, the control signal is synchronized with a clock signal having the first frequency. By communicating the current set of data values to the first set of registers, a hardware component (e.g., a CPU) can access the current set of data values without restriction.

Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction

A technique for encoding macroblocks of a frame is provided which includes switching a coding decision for a macroblock from a non-intra decision to a skip macroblock decision when the absolute prediction error for the macroblock is less than a prediction error threshold and the magnitude of the motion vector for the at least one macroblock is less than a motion vector threshold. In one embodiment, the prediction error threshold is multiple programmable prediction error thresholds, which are for comparison with the absolute luminance and chrominance summation components and the maximum luminance and chrominance difference values. The motion vector threshold may be a preset value when the macroblock is to be predictive coded, and may be the magnitude of the motion vector of the previous macroblock when the macroblock is to be bi-directionally encoded.

Macroblock coding technique with biasing towards skip macroblock coding

A technique is provided for programmably vertically filtering pixel values of frames of a sequence of video frames. The technique includes separating luminance components and chrominance components of the pixel values within a vertical filter buffer, then vertically filtering luminance components of the pixel values using programmable luminance filter coefficients, and vertically filtering chrominance components of the pixel values using programmable chrominance filter coefficients. The filtered luminance component data and filtered chrominance component data is subsequently merged onto a single luminance/chrominance bus for further filtering and/or encoding. The luminance and chrominance filter coefficients are programmable and may be changed dynamically and repeatedly at picture boundaries. In one embodiment, the programmable vertical filter includes a four tap luminance component filter and a five tap chrominance component filter.

Programmable vertical filter for video encoding

Simultaneous vertical spatial filtering and chrominance conversion is achieved with reduced data buffering and simplified filtering circuits by using a single filter stage and hybrid filter coefficients. Data latency is reduced and performance requirements are reduced while avoiding critical signal propagation paths. The filter and buffers are fully compatible with any scan format having consecutively presented lines of image data, including both progressive and interlaced scan formats.

Simultaneous vertical spatial filtering and chroma conversion in video images

A technique is provided for encoding macroblocks of a frame of a sequence of video frames initially employing luminance data only to analyze temporal redundancy of the macroblocks within the frame. Upon deciding to code at least one macroblock as a non-intra macroblock, the technique includes considering whether to switch the coding decision for the at least one macroblock from non-intra to intra by evaluating chrominance data of the at least one macroblock. The evaluating of the chrominance data can include determining whether chrominance difference data, obtained by comparing chrominance values of a current macroblock with a reference macroblock, is greater than a user set chrominance difference threshold, and if so then the technique includes switching the macroblock coding decision. As a further qualification, the switching might occur only if the chrominance difference data is also greater than the corresponding luminance difference data.

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Essex Junction, VT, United States of America

John M Sutton