International Business Machines Corporation

Globespan Virata Corporation

John M Ross

Louis L Hsu

Toshiaki Kirihata

George K Woodworth

Dmitry G Netis

Brian Horng

L Brian Ji

Peter D Keller

Benedict A Itri

Devin K Ng

James J Zhao

Andrew C MacAllister

Stuart B Ross

Michael A Scarcella

A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.

Filter tuner system and method

Digital latency shift communication problems from a driver chip to a receiver chip are overcome by scheduling a data output latency, a data input latency, a data output command, and/or a data output command, such that data outputted by the driver chip is received by the receiver chip at the correct time. A digital shift detection circuit detects the offset of the actual latencies from predetermined latencies. The offset of the latency is fed back to the scheduling circuit to override the predetermined latencies and/or command inputs that control the chip. The offset can be directly back-fed to the chip driver or chip receiver to compensate for digital shifts. Digital shift detection is achieved by measuring actual latencies with a manufacturing stand-alone tester, or with a built-in tester integral to the system. The digital shift detection predicts the conditions that create a digital shift by way of a mathematical model.

Rescheduling data input and output commands for bus synchronization by using digital latency shift detection

A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Digital frequency divider

An integrated circuit memory device comprising an arrangement of physical wordlines, WL0-WLn, arrange such that each wordline is addressed by a plurality of pairs, An&plus;1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm&plus;1, Wlm&plus;2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being &ldquo;00,&rdquo; &ldquo;01,&rdquo; and &ldquo;10&rdquo; respectively.

Binary to binary-encoded-ternary (BET) decoder using reordered logic

Underwater fishing light

An asynchronous multiphase switching method and apparatus are disclosed which transfers a system load between two asynchronous AC power sources in an improved manner. It operates as a make-before-break switch to provide uninterrupted power to the system load during the transfer while minimizing voltage and current fluctuations. The control circuitry allows energy to be supplied to the load during the transition without allowing current to flow between the power sources. A matrix of SCRs is used to transfer the load between the two power sources. The switches to be gated are determined by the relative timing relationships of the existing and takeover voltage waveforms. By altering the pattern of the switches which are gated and by controlling the direction of energy flow, the transition can be made between the power sources without interruption of power.

Asynchronous multiphase switching gear

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Matawan, NJ, United States of America

John M Ross