Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Nxp B.v.

Other

Denso Corporation

John M Pigott

Randall C Gray

William Ernest Edwards

Robert B Jarrett

Paul T Bennett

Olivier Trescases

Hendrik Johannes Bergveld

Fred T Brauchler

Gerard Villar Piqué

Alaa Eldin Y El Sherif

Ira G Miller

Byron G Bynum

Mike Robert Garrard

Joachim Kruecken

John Matthew Hall

Peter Hans Schulmeyer

Mojtaba Ashourloo

Vishnu Khemka

Thierry Sicard

Trevor M Newlin

John Ryan Goodfellow

Thomas Jeffrey Reiter

Ondrej Pauk

Mahraj Sivaraj

Kyle James Wollschlager

Nameer Ahmed Khan

Pragya Priya Malakar

Venkata Raghuram Namburi

Joseph Staudinger

Ronghua Zhu

Stephen P Robb

Gustavo James Mehas

Stefano Pietri

Amitava Bose

Ljubo Radic

Ganming Qin

Krishna Thakur

Geoffrey W Perkins

Divya Tripathi

Meng Wang

Robert Van Veldhoven

Ibrahim S Kandah

Tanuj Saxena

Norman Lee Owens

Darrel R Frear

John R Qualich

Thierry Michel Alain Sicard

Philippe Perruchoud

Benjamin R Davis

Jeffrey J Braun

Ricardo Goncalves

Carl Emil D'Acosta

Guillaume Mouret

Jaswinder S Jandu

Vivek Gupta

Liang Qiu

Randall T Wollschlager

Michael J Zunino

Damon Peter Broderick

Sergey Sergeevich Ryabchenkov

Stephan Ollitrault

Gerrit Van Der Horn

Karl R Heck

Ivan Victorovich Kochkin

Ryo Shimizu

Paul E Fletcher

Peter J Pinewski

Tristan Bosvieux

Percy Edgard Neyra

Zhichen Zhang

Chuanzheng Wang

Hamada Ahmed

Hang Fung Yip

Sadique Mohammad Iqbal

Anubhav Srivastava

Qilin Zhang

Richard Visee

Craig M Aykroyd

T Jeffrey Reiter

Michael Jennings

Raviraj Dattatraya Vader

Ahmed E Hashim

Jeremy Guillermand

Valerian Mayega

Charles R Powers

Kevin S Anderson

Philipe J Perruchoud

Brent D Rogers

Eric J Toulouse

Ricardo Takase Goncalves

A method, power converter and controller are disclosed for controlling a power converter having a main converter connected between a first input voltage and a ground and having a main output at an output terminal, an auxiliary converter connected between a second input voltage and the ground and having an auxiliary output, an output capacitor connected between the main output terminal and a ground, and an auxiliary capacitor connected between the auxiliary output and the main output terminal; and a controller; the method comprising: operating the main converter at a first frequency, operating the auxiliary converter at a second frequency; controlling the main converter to control the voltage at the auxiliary output; and controlling the auxiliary converter to control the voltage at the main output.

Control of two-stage dc-dc converter

Disclosed are a controller and power converter having a main buck converter connected between a first input voltage and ground and having a main output, a bidirectional auxiliary converter connected between a second terminal and ground and having an auxiliary output connected to the main output, an output capacitor, and an auxiliary capacitor connected between the second terminal and the ground for providing a second terminal voltage at the second terminal; the controller comprising: first control circuit configured to operate the main converter at a first frequency; and second control circuit configured to operate the auxiliary converter at a higher frequency; the first control circuit being further configured to operate the main converter in dependence on the second terminal voltage; and the second control circuit being further configured to operate the auxiliary converter to control the voltage at the main output terminal.

Control of auxiliary-assisted DC-DC converter

Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.

Frequency-regulated oscillator circuit

A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference Vsignal to a voltage feedback signal V, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal Vfor input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fby the trimming resistor.

Self-biased, closed loop, low current free running oscillator

Embodiments of a power stage for a direct current (DC)-DC converter and a DC-DC converter are disclosed. In an embodiment, a power stage for a DC-DC converter includes an input terminal from which input power of the DC-DC converter with an input DC voltage is received, a high-side segment connected between the input DC voltage and an output signal of the power stage, and a low-side segment connected between the output signal of the power stage and ground. At least one of the high-side segment and the low-side segment includes stacked transistors having isolation terminals that are biased to reduce substrate injection.

Isolation connections for high-voltage power stage

A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.

Transistor with integrated short circuit protection

Embodiments of a multi-mode transition circuit for a DC-DC converter and a DC-DC converter are disclosed. In an embodiment, a multi-mode transition circuit for a DC-DC converter includes a transconductance amplifier operably connected to a first resistor-capacitor (RC) network and switches, a comparator operably connected to a second RC network, where the first and second RC networks are operably connected to a reference voltage, a multiplexer operably connected to the transconductance amplifier and the comparator, and an operation mode selector configured to enable or disable the transconductance amplifier and turn on or off the switches in a sequence when transitioning between a pulse-frequency modulation (PFM) mode and a pulse-width modulation (PWM) mode.

Multi-mode transition for a DC-DC converter

An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.

Amplifier with low component count and accurate gain

A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.

Bandgap reference compensation circuit

A switching power regulator and method for recovering the regulator from an unregulated state while preventing overshoot of an output voltage is provided. The regulator includes a dropout detector, a sample-and-hold circuit, a voltage offset circuit and a soft start circuit. When the regulator enters an unregulated state, the dropout detector detects when a pulse width modulation (PWM) signal stops toggling. The sample-and-hold circuit and soft start circuit are used to effectively clamp the voltage at the output of an error amplifier. This causes the output of the error amplifier to regulate around a desired voltage so that the regulator recovers from the unregulated state with little or no overshoot of the output voltage. In another embodiment, a method for recovering from the unregulated state is provided.

Switching power regulator and method for recovering the switching power regulator from an unregulated state

There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw, Vsw, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw[n&#x2212;1], Vsw[n&#x2212;1]) and in a next subsequent operating cycle (Vsw[n], Vsw[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Fault detection in hybrid DC-DC power convertors

A level shifter comprising: a translation circuit having two input lines and two output lines and configured to receive a differential signal in a low-voltage domain on the two input lines and provide a second differential signal, being a copy of the first differential signal, in a high-voltage domain on the two output lines; and a combiner circuit configured to convert the second differential signal into a single-ended signal at a high-voltage shifter output; wherein the combiner circuit comprises a two-input Muller C-element circuit wherein one input is inverted. Corresponding methods are also disclosed.

Level shifter and a method of level shifting a signal

Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Distributed control of a multiphase power converter

A method for current limiting an operational amplifier includes sensing a first current through a first branch of the operational amplifier. The first branch conducts the first current from a limited current supply connected to an operational amplifier output. The first current is compared to a reference current to generate a regulation signal. A variable current source is controlled with the regulation signal. An output current of a transconductance amplifier is limited with the variable current source to limit the first current in response thereto.

Operational amplifier with current limiting circuitry

An input protection circuit () and associated method are disclosed for protecting a circuit input (V) from positive and negative overvoltages at an input voltage (V) with a high-voltage PMOSFET (P) having a gate, a drain connected across a zener diode (ZD) to the gate, and a source connected to receive an input voltage; a blocking FET (N) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD) to the gate, and a drain connected to a source follower node and a level shifter circuit () connected between the drain of the high-voltage PMOSFET and the source follower node.

High speed wide dynamic range input structure

Growing community of inventors

Phoenix, AZ, United States of America

John M Pigott