National Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Develco, Inc.

John M Pierce

William I Lehrer

Ali A Iranmanesh

Dah-Bin Kao

Albert M Bergemont

James Montague Cleeves

Richard B Merrill

Michael E Thomas

James E Opfer

Sung T Ahn

Kenneth J Radigan

Peter Henry Renteln

C S Teng

Thomas Keyser

Sung Tae Ahn

Lawrence E Valby

An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Method of planarizing integrated circuits with fully recessed isolation

Problems forming silicided and nonsilicided structures on the same silicon substrate are overcome utilizing a spacer oxide masking technique. A protective spacer oxide layer is deposited over the entire silicon substrate surface, and a silicide exclusion photoresist mask is selectively developed to permit etching of the spacer oxide layer in unmasked regions where silicides are expected to be formed. Areas of silicon substrate revealed by etching of the spacer oxide layer are exposed to silicide-forming metals, and these silicide-forming metals react with the silicon substrate to produce silicides. Spacer oxide remaining in masked regions prevents formation of silicides in those regions.

Method for protecting nonsilicided surfaces from silicide formation

A method of fabricating external contacts in an integrated circuit structure utilizes chemical mechanical polishing (CMP). The structure includes an active device substrate region defined by field oxides. First and second diffusions formed in the active region define a substrate surface region therebetween. In accordance with the method, a layer of amorphous or polycrystalline silicon is formed in contact with the diffusion regions, subjected to a chemical mechanical polishing (CMP) step and then etched to form external contacts. The process flow can be applied to CMOS technologies and adapted to bipolar technologies to provide a BiCMOS flow.

Method of fabricating self-aligned contacts and local interconnects in

The process for forming a layer of metal silicide over polysilicon structures, such as gates and interconnect lines, is simplified by forming a layer of insulation material over the polysilicon structures, removing the layer of insulation material until the layer of insulation material is substantially planar and the thickness of the insulation material over the polysilicon structures is within a predetermined thickness range, etching the planarized layer of insulation material until portions of the polysilicon structures are exposed, depositing a layer of metal over the resulting structure, and then reacting the metal layer with the polysilicon structures to form the layer of metal silicide.

Self-aligned polycide process that utilizes a planarized layer of

A series of self-aligned, intermediate strips of conductive material, which contact each of the drain regions in a corresponding number of columns of drain regions in a flash electrically programmable read-only-memory (EPROM), are formed as a thick layer of planarized polysilicon. By utilizing intermediate strips of conductive material which are formed from a thick layer of polysilicon, the formation of cracks or voids in the intermediate strips of conductive material can be eliminated.

Method of making increased-density flash EPROM that utilizes a series of

A method is disclosed for forming MOSFET devices on a semiconductor substrate including steps of depositing layers of polysilicon, dielectric, and polysilicon again. Each polysilicon layer is planarized after it is deposited. The dielectric layer is patterned and etched to delineate active regions and interconnect grooves. After the second polysilicon layer is planarized, the material in the active region is patterned and etched to form a gate and source and drain areas. The appropriate areas of the active region are doped as necessary to form the source and drain.

Method of manufacturing a fully planarized MOSFET and resulting structure

A method is provided for planarizing the surface of an integrated circuit over a metal interconnect layer. Metal interconnect lines and surrounding regions of a partially fabricated integrated circuit are first coated with a thin layer of dielectric substantially free of voids and then coated with a polysilicon layer. The polysilicon layer is planarized back to the level of the dielectric layer on top of the interconnects, providing a substantially planar surface for subsequent fabrication steps including deposition of a second dielectric layer and an overlying metal layer.

Method for planarizing the surface of an integrated circuit over a metal

A polishing pad and a method for polishing semiconductor wafers. The polishing pad includes a polishing layer and a rigid layer. The rigid layer adjacent the polishing layer imparts a controlled rigidity to the polishing layer. The resilient layer adjacent the rigid layer provides substantially uniform pressure to the rigid layer. During operation, the rigid layer and the resilient layer apply an elastic flexure pressure to the polishing layer to induce a controlled flex in the polishing layer to conform to the global topography of the wafer surface while maintaining a controlled rigidity over the local topography of the wafer surface.

Polishing pad and method for polishing semiconductor wafers

An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Means of planarizing integrated circuits with fully recessed isolation

An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Process for making isolated semiconductor structure

Product for making isolated semiconductor structure

A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

Method and apparatus for low pressure chemical vapor deposition

A method for impregnating copper into aluminum interconnect lines on a semiconductor device is disclosed. In a first embodiment, an interconnect pattern is formed on an aluminum layer by etching while the aluminum is substantially free from copper, and the copper is thereafter introduced to the formed interconnect lines. In a second embodiment, copper is introduced to the aluminum layer prior to formation of the desired interconnect pattern. The copper-rich layer is removed from the areas to be etched prior to etching. The method facilitates chlorine plasma etching of the aluminum which is inhibited by the presence of copper. The method is also useful with various wet etching processes where the formation of a copper-rich layer is found to stabilize the aluminum layer during subsequent processing .

Impregnation of aluminum interconnects with copper

A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Smooth glass insulating film over interconnects on an integrated circuit

A process for suppressing electromigration in conducting lines formed on integrated circuit structures includes the steps of forming the conducting lines on the integrated circuit structure and heat treating the lines to cause the average grain size in the lines to become larger than the width of the conducting lines.

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Palo Alto, CA, United States of America

John M Pierce