Texas Instruments Corporation

John M Muza

Heino Jean Wendelrup

James R Hellums

Brett Earl Forejt

Zhengwei Zhang

Roberto Sadkowski

Martin Sallenhag

A differential circuit with linearity correction loop includes a main differential amplifier , and a correction amplifier having inputs coupled to the outputs of the main differential amplifier through feedback paths. The output signals from the correction amplifier are combined with the inputs to the main amplifier such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Differential circuit with a linearity correction loop

A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Capacitor compensation in miller compensated circuits

A microphone bias current detection circuit includes: a microphone circuit ; an amplifier having a first output and a second output, the first output is coupled to the microphone circuit for providing a bias current to the microphone circuit , the second output provides a sampled current I proportional to the bias current; a first switch having a first end coupled to the second output of the amplifier ; a resistor having a first end coupled to a second end of the first switch ; and a second switch coupled between the first end of the resistor and a reference current source.

Microphone bias current measurement circuit

A single-ended, ultra low voltage class AB power amplifier ( ) including an input gain stage ( ), output gain stage ( ), a quiescent current control circuit ( ) and a output stage bias reference circuit ( ). The input gain stage ( ) includes differential inputs (IN , IN ) and differential outputs (A , B ). The output stage ( ), having control transistors, connects to each differential output (A , B ) of the input stage ( ). and a quiescent current control circuit ( ) deriving common mode feedback control signal (V ) from the differential outputs (A , B ) and voltage bias node (D ). A quiescent current control circuit ( ) derives the common mode feedback control signal (V ) to maintain the voltage of the input gain stage transistors (M , M ) at a desired level. The quiescent current control circuit ( ) uses the bias voltage (V ) supplied by an output stage bias reference ( ) coupled thereto for generating the control signal (V ) to be applied to the gates of the input stage transistors (M , M ), thereby maintaining the quiescent current of the output transistors (M , M ) at a desired value.

Single-ended, ultra low voltage class AB power amplifier architecture having a common-mode feedback quiescent current control circuit

The two-stage power amplifier includes: a first stage transconductor ; and a second stage having at least two parallel output branches supplying current to an output node , each output branch has an input coupled to an output of the first stage transconductor

CMOS power amplifier for driving low impedance loads

A low-pass filter circuit includes: a first compound transistor device ( ) and ( ) coupled between an input node ( ) and an output node ( ); a first transistor ( ) coupled to the input node ( ), a gate of the first transistor ( ) is coupled to a drain of the first transistor ( ); a second compound transistor device ( ) and ( ) coupled between a gate of the first compound transistor device ( ) and ( ) and the gate of the first transistor ( ); a second transistor ( ) coupled to the first transistor ( ) and having a gate coupled to a gate of the second compound transistor device ( ) and ( ), the gate of the second transistor ( ) is coupled to a drain of the second transistor ( ); a current source ( ) coupled to the drain of the second transistor ( ); a first capacitor (C ) coupled to the output node ( ); and a second capacitor (C ) coupled to the gate of the first compound transistor device ( ) and ( ).

Low-pass filter with improved high frequency attenuation

A method and circuit (,) for tuning a G,/C filter. A first circuit portion includes a variable current source (,) having a plurality of transistors M,through M,coupled to switches SWA through SW,. The output capacitor C,is calibrated iteratively by compensating a calibration capacitor C,with the variable current source to tune the G,/C filter. The transconductance G,is dependent on a precision external resistor R,rather than on internal resistors of the G,/C filter. An algorithm (,) performs the iterative calibrations for the G,/C filter. The invention is particularly useful for mixed signal or analog circuits.

Tuning method for Gm/C filters with minimal area overhead and zero operational current penalty

The distortion correction circuit includes: a main amplifier,having a first resistor,coupled from an output of the main amplifier,to a first input of the main amplifier,, and a second resistor,coupled between the first input of the main amplifier,and a first input signal node; a correction loop amplifier,having an output coupled to a second input of the main amplifier,, an output of the main amplifier,coupled to a first input of the correction loop amplifier,, a second input of the correction loop amplifier,coupled to a second input signal node.

Distortion correction loop for amplifier circuits

A microphone bias amplifier circuit (,) and method for biasing a microphone with an amplifier circuit. The amplifier circuit (,) has an input stage (,) coupled to an output stage (,). The output stage (,) includes a first transistor (M,) coupled to a feedback loop (,) provides a variable source current (,) to the first transistor (M,) and the output stage output V,. The feedback loop (,) includes an amplifier (,) coupled to the first transistor (M,) and a first current source (I,) conducted through a second transistor (M,) and coupled to the amplifier (,). The amplifier (,) controllably drives a third transistor (M,) coupled to a voltage source (AVDD) to generate the variable current source (I,). The gates of the first (M,) and second (M,) transistors are coupled together and driven by the input stage (,). The third transistor (M,) of the feedback loop (,) provides the variable source current (I,) to the first transistor (M,), whereby the current conducted by the first and second transistors (I,, I,) is equal, and the remainder (I,-I,) of the variable source current (I,) is provided to the load of the output stage (,).

Efficient microphone bias amplifier with high output voltage/current capability and excellent PSRR

A low noise, low current, high bandwidth differential amplifier circuit (,), including a first amplifier (,) driving a first transistor X,and having a first current source I,coupled to an input of the first amplifier (,). A first feedback resistor R,is coupled between the first current source I,and the first transistor X,, and a second resistor R,is coupled to the first resistor R,. A second amplifier (,) drives a second transistor X,, and has a second current source I,coupled to an input of the second amplifier,A third feedback resistor R,is coupled between the second current source I,and the second transistor X,. A fourth resistor R,is coupled to the third resistor R,. The first R,and third R,feedback resistors are driven by the first I,and second I,current sources rather than by the first (,) and second (,) amplifiers, respectively, allowing the first and second amplifiers (,) to be single stage amplifiers. A buffering stage (,) having a high pass filter may be coupled to the output signal. The invention is particularly useful for applications such as mixed signal or analog circuits.

Current efficient, ultra low noise differential gain amplifier architecture

An ultra low voltage CMOS, class AB power amplifier has internal compensation using only parasitic gate capacitance.

Ultra low voltage CMOS class AB power amplifier with parasitic capacitance internal compensation

An analog clipping circuit includes: a main amplifier 20; a feedback resistor 26 coupled between a first input of the main amplifier 20 and an output of the main amplifier 20; a first current source 50 coupled in parallel with the feedback resistor 26; a first clipping amplifier 42 coupled to the first current source 50 for controlling the first current source 50, the first clipping amplifier 42 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a first reference node; a second current source 54 coupled in parallel with the feedback resistor 26; and a second clipping amplifier 44 coupled to the second current source 54 for controlling the second current source 54, the second clipping amplifier 44 having a first input coupled to an output of the main amplifier 20 and a second input coupled to a reference node.

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Plano, TX, United States of America

John M Muza