Chrysler Motors Corporation

Chrysler Corporation

John M McCambridge

Frederick O Miesterfeld

Ronald E Fassnacht

Jerry M Nasiadka

William V Luitje

Richard A Halter

David A Wagner

A communication system for controlling remote devices within a vehicle is provided. The communication system includes a master module for generating a command message, and a remote module for executing the command message and generating a response message. A data bus provides bidirectional communication between the master module and the remote module. The communication system also includes a message frame for communicating data between the master module and the remote module, the message frame includes the command message generated by the master module for execution by the remote module, and the message frame includes the response message generated by the remote module for providing feedback to the master module.

J1850 application specific integrated circuit (ASIC) and messaging technique

A power supply start up booster circuit for providing an increased startup voltage for a switch mode control integrated circuit including a boost portion for combining a first input voltage that has a predetermined minimum value and a second input voltage that transitions from 0 volts to the predetermined minimum value to make a minimum threshold voltage, a control portion having an integrated circuit for using the minimum threshold voltage to temporarily provide a voltage input at the integrated circuit, and an output portion for providing a permanent voltage input at the integrated circuit and an output supply voltage to an external circuit.

Power supply start up booster circuit

A synchronization circuit synchronizes asynchronous parallel byte words input data with synchronous parallel byte output data so as not to glitch or interrupt required regular flow of synchronous data to end user devices.

Asynchronous-to-synchronous parallel word transfer circuit for

A bus receiver power-up synchronization circuit synchronizes the receipt of parallel data messages transferred asynchronously as three byte words preceded and succeeded by idle bytes so as to receive complete and not partial messages. Also, the receiver scrutinizes the messages for faults and for too many or too few bytes.

Bus receiver power-up synchronization and error detection circuit

Combinational logic circuits are used with a temporary storage device holding data bytes to detect improper bits in both the lower and upper nibbles of the bytes. Combinations of bit patterns derived from both nibbles permit flagging the occurrences of a variety of bit errors existing in sequentially transmitted parallel data bytes.

Improper bit combination detection circuit

A method and firmware/hardware system for updating an analog odometer using a pulse rate rather than an absolute number of updating pulse signals. The pulse rate is developed from a number that represents an accumulation of a series of pulses that represent distance traveled by a vehicle during a chosen interval.

Vehicle serial bus, mechanical instrument cluster odometer therefor

A data reception device extracts serial, unipolar data from both current mode and voltage mode differential transmission links and converts such data into parallel data suitable for use by end-user equipment.

Serial to parallel data conversion system

A half-bridge driver circuit extends the duration of recirculating decaying currents in an inductance type indicating gauge after source voltage is cutoff. An inverter circuit controls a source transistor to provide a lower resistance path for the decay current than provided by the suppression diodes of the half-bridge driver.

H-driver

A digital pulse width modulator for generating output frequencies with adjustable pulse widths that can be controlled by a microcomputer interface. A method to perform a DPWM chip select and to control the latching, shifting and counting of DPWM counters and registers is also presented. This allows the traditional uses of PWMs to enter the realm of microcomputer systems.

Method for chip selection and counting in a digital pulse width

In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, a method to transmit and receive data in a buffered serial peripheral interface (SPI) mode of operation in conjunction with a method of arbitrating data on the data bus.

Method for buffered serial peripheral interface (SPI) in a serial data

In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, a method to transmit and receive data in an SPI mode of operation in conjunction with a method of arbitrating data on the data bus.

Method for serial peripheral interface (SPI) in a serial data bus

The aim of the Chrysler Collision Detector (CCD) Bus System is to allow multiple microprocessors to easily communicate with each other over a common pair of wires (called a bus) using a scheme similar to a telephone party line. All microprocessors connected to the bus are able to receive all messages transmitted on the bus. Any microprocessor with a message to transmit on the bus waits until any current user is finished before attempting to use it. Whenever the bus is available, its use is allocated on a first-come, first serve basis (i.e., whichever microprocessor first begins transmitting its message on the bus after any previous message finishes gets the use of the bus). If, however, multiple microprocessors attempt to begin transmitting their messages on the bus at exactly the same time, then the message with the highest priority wins the use of the bus. All messages have unique message priority values and each message is transmitted by only one microprocessor. The subject invention provides the ability to communicate with a SCI port, a SPI port or a buffered SPI port. This allows communication with any device configured with any one of these ports, all on the same bus.

Serial data bus for serial communication interface (SCI), serial

A method of blocking data transmission from a user microprocessor to a data bus utilizing arbitration and collision detection in a data bus interface integrated circuit utilizing a Serial Communication Interface (SCI) port on the user microprocessor.

Method of data arbitration and collision detection in a data bus

A bus interface integrated circuit is presented which utilizes an arbitration detector, a collision detector and a contention permitting differential transceiver to work with a serial communication interface port on a microprocessor to determine between contending messages which message gains access to the communication bus by using the value or priority of the ID byte without losing bus time.

Serial data bus for intermodule data communications

A digital pulse width modulator for generating output frequencies with adjustable pulse widths that can be controlled by a microcomputer interface. This allows the traditional uses of PWMs to enter the realm of microcomputer systems.

Growing community of inventors

Northville, MI, United States of America

John M McCambridge