Wang Laboratories, Inc.

John M Martins

James B MacDonald

Robert R Trottier

Dennis J Kayser

Apparatus and method for reconfiguring a memory in a data processing system to increase the rate of information transfer between system memory and processor. The system memory is comprised of a plurality M of memory banks, each having a separate data output path. In a first configuration a memory controller addresses the memory banks sequentially to read from one address location at a time. The memory is reconfigured by an address translator providing addresses addressing M banks in parallel, so that M locations are read in each read operation, and a bus reconfiguration multiplexer which reconfigures the bank output busses in parallel and selects one or more bank output busses as the memory output to the system processor. In a further embodiment, a cache is connected in parallel with the parallel bank outputs for storing information appearing upon the non-selected bank output busses paths for subsequent transfer to the memory output in a subsequent reading from memory of previously read but non-selected information.

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Wilmington, MA, United States of America

John M Martins