Compaq Computer Corporation, Inc.

Other

Computer Corporation

John M MacLaren

Alan L Goodrum

Paul R Culley

Christopher J Pettey

Brian S Hausauer

Usha Rajagopaian

A computer system includes an apparatus which enables transactions directed to a particular target device such as one situated inside a bridge to be shunted directly to the device without requiring that the transaction actually proceed to the device through a bus on which the device is located. However, the transaction may, in fact, also be run on the bus on which the device is located, the ID select for the target device may be masked. In this way, it is possible to run transactions to a particularly critical device even when the bus on which it is located is, for one reason or another, not operating.

Fault tolerant computer system

A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher priority transaction and transactions initiated before the higher priority transaction, and a controller that selects transactions from the execution queue to be completed on one of the data buses.

Ordering transactions

A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer.

Prefetching data in response to a read transaction for which the

A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

Bridge circuit comprising independent transaction buffers with control

Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

Multi-threaded bus master

A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

Storing data associated with one request while continuing to store data

An apparatus and method for determining the types of expansion cards connected to the expansion slot connectors of a computer system. Detect signals are provided to decode logic for determining the types of expansion cards connected to the computer system. If the expansion cards are compatible the decode logic produces an output power supply signal that indicates what the voltage level should be for the power supply to the cards. If the cards are incompatible, the decode logic may not provide power to any of the cards or only provide power to some of the cards that are compatible. For computers that allow expansion cards to connect to the computer while the computer is powered on, hot-plug logic cooperates with the decode logic to establish power and communication with newly connected interface cards. The connectors in the computer do not include keys and thus interface cards without keys, as well as cards with different types of key arrangements can be connected to and communicate with the computer. A removable keyed adapter can be mated with the expansion slot connectors to effectively provide keys to the expansion slot connectors to ensure reliable connections between the interface cards and expansion slot connectors. The adapters can be keyed in variety of arrangements to match whatever keying arrangements are included on the interface cards. In an alternative embodiment, voltage drops are provided to quick switches to ensure signaling compatibility between different card types. Further, all expansion slot connectors can be keyed for only a subset of the possible card types available and thus reduce the logic necessary to ensure compatibility.

Computer expansion slot and associated logic for automatically detecting

A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

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Cypress, TX, United States of America

John M MacLaren