Sun Microsystems, Inc.

Toshiba America Electronic Components, Inc.

John M Lo

Charles T Cheng

A method and apparatus for determining whether a TCP packet lands in-zone or out-of-zone of a TCP sequence space. An anchor representing the TCP sequence number of the last TCP data byte, plus one, is updated each time a TCP data packet is received. When a new TCP packet is received, the most significant bit, bit [], is extracted from the anchor. A two-bit value is formed by adding 1 to the extracted bit. This two-bit value is pre-pended to bits [30:0] of the anchor, as bits [32:31], to produce a 33-bit test value. Then, the sequence number of the last TCP byte of the received packet is then compared to the anchor and the test value. If the sequence number is greater than or equal to the anchor, and less than the test value, the packet lands in-zone and may be processed normally.

Method and apparatus for determining the landing zone of a TCP packet

A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Method and apparatus for avoiding collisions during packet enqueue and dequeue

A method and apparatus for facilitating the determination of a status of an asynchronous memory (e.g., how full or empty the memory is). A write pointer to the memory is maintained in a first clock domain; a read pointer is maintained in a second clock domain. The pointers are maintained in a non-binary code format promoting minimum bit transitions as the pointers increment (e.g., Gray code). Each pointer is transmitted to the other clock domain through synchronizers. Each synchronizer comprises multiple sets of D flip-flops. In each clock domain, the write pointer and read pointer values are converted to mathematically useful formats (e.g., binary), and their difference is calculated. The difference indicates how much space in the memory is or is not used, and may be compared to a non-zero threshold.

Method and apparatus for determining a status of an asynchronous memory

A method and apparatus are provided for determining a suitable inter-packet gap (IPG), or a suitable extension to be added to a default IPG as a packet is processed. The apparatus includes an adder to add an incremental measure of a packet to an existing measure and produce a new measure (e.g., in bytes). The apparatus further includes a comparator which, if the new measure exceeds a programmable threshold (e.g., a stretch ratio), issues a signal to increase the IPG and decreases the new measure by the threshold. The current measure is then stored (e.g., in a register) for addition to the next incremental measure. A counter tracks the number of signals received before the end of the packet, at which time the total is forwarded to a component configured to insert or apply the IPG and the counter is reset for the next packet.

Variable length inter-packet gap

An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by high throughput error checking to verify the integrity of the communicated data. One approach of improving the performance of cyclic redundancy code generation hardware that can save money and development time is to combine multiple cyclic redundancy code circuits to perform the error checking. Data received is processed across the multiple cyclic redundancy code circuits. Future cyclic redundancy code circuits can also be combined according to this approach.

Apparatus and method for applying multiple CRC generators to CRC calculation

A one's complement adder uses two two's complement adders, both of which are coupled to receive first and second addends at their addend inputs, however the first two's complement adder is adapted to output a first sum that is the one's complement sum that would result if no carry occurred upon addition of the first and second addends and the second two's complement adder is adapted to output a second sum that is the one's complement sum that would result if a carry did occur. A selector selects one of the first sum and the second sum as its output (and the output of the one's complement adder) based on whether or not a carry occurred. The indication of whether or not a carry occurred or not can be determined from the carry output of the first complement adder, with the first sum effected by setting the carry input for the first two's complement adder to &ldquo;0&rdquo; (no carry in) and the second sum effected by setting the carry input for the second two's complement adder to &ldquo;1&rdquo; (carry in). The selector can be a multiplexer with a select input coupled to the carry output of the first two's complement adder.

High speed one's complement adder

An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit in the event the value of the current bit is 1 and the value of the left adjacent bit is 0. In one specific embodiment, the apparatus employs a multiplexer and a single-bit register with a feedback as a one bit detection and correction circuit.

System for correcting an illegal addressing signal by changing a current bit from one to zero if a bit immediately left adjacent to the current bit is zero

A FIFO memory apparatus of the present invention includes an array of registers including a plurality of stacked subarrays. A first plurality of multiplexers is provided including one multiplexer for receiving data from each one of the subarrays. A second plurality of multiplexers is also provided each for receiving data from two other multiplexers. One of the second plurality of multiplexers supplies an output for the FIFO memory apparatus, while each of the others, in pairs, supply other multiplexers of the apparatus. The invention uses a four-way interleaved memory architecture for pre-decoding the FIFO read pointer and driving out data from one of the sixteen deep 32-bit wide registers, in advance. In this way, the final stage of the timing critical path is from the Q output of a toggle flip-flop to a two-to-one multiplexer and output buffer. This Q output of the toggle flip-flop is the least significant bit (LSB) of a four-bit counter used to select one of the 16-bit deep, 32-bit wide registers of the FIFO.

Four-way interleaved FIFO architecture with look ahead conditional

A high modulus counter is provided for receiving a counter enable (CE) signal which switches between digital states. The counter is a single load conditional look ahead counter having a carry chain isolated from a timing critical path. The counter includes one toggle flip-flop for receiving the CE signal. The flip-flop has a first output and a second output. The first output and the second output are connected to an even counter and an odd counter, respectively. Both the output of the first counter and the output of the second counter are received by each of a plurality of multiplexers which are controlled by the first output of the toggle flip-flop. In this way, the high modulus counter outputs and increments the pointer signals of the odd counter and the even counter, alternatively. The even and odd internal counters are initially set at zero and one, respectively, and each increments by two. A second flip-flop may additionally receive the external CE signal for synchronization. The outputs of the flip-flop may also be received by a pair of AND gates, the outputs of which are received by a pair of PLS generators. The two PLS generator outputs then serve as the respective CE signals for the odd and even counters.

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Fremont, CA, United States of America

John M Lo