Parthus Ireland Limited

Ceva Services Limited

Parthus Technologies Plc

Amadala Limited

John M Horan

John G Ryan

John Ryan

Niall O'Donovan

Ciaran Cahill

Joe Duigan

Tholom Kiely

Cyril Lahuec

Mark M Smyth

Mark Smyth

Kay Hearne

David J Foley

Steven Dunphy

Hooman Reyhani

Charge from a charge pump of a PLL is dumped to a loop filter of the PLL. The dumped charge is temporarily stored in a capacitor, between the charge pump and the loop filter. A voltage of the capacitor is shifted, while temporarily storing the dumped charge. Other embodiments are also described and claimed.

Phase locked loop with floating capacitor boost circuit

A filter couples an output of a phase detector to an input of a voltage controlled oscillator. The filter has a first capacitor and a switch capacitor resistor that is in series with the first capacitor, between the first capacitor and the output of the phase detector. The switch capacitor resistor is to display a resistance that is obtained by switching back and forth a second capacitor to the first capacitor and to the phase detector output. Other embodiments are also described and claimed.

Phase locked loop with a switch capacitor resistor in the loop filter

A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.

Method and apparatus for automatically generating a phase lock loop (PLL)

A method and a digital circuit for synthesizing an input signal to produce an output signal are provided. The circuit includes a delay unit with a delay input and a delay output, a switch, and a controller. The selectively switch routes the input signal to the delay input whereafter the switch routes the delay output to the delay input. The controller controls the delay unit in response to the input signal and the output signal. A counter is provided to count a predetermined number of times the delay output is routed to the delay input whereafter the input signal is routed to the delay input to trigger the delay input. The digital circuit synthesizes the input signal to define a Delay-Locked loop (DLL) in which the delay unit is a voltage controlled delay line (VCDL). The invention extends to a computer program product executing the method and to an embedded circuit including the digital circuit.

Digital circuit for, and a method of, synthesizing an input signal

A method is described that level shifts a differential signal to produce a first signal and level shifts the logical inverse of the differential signal to produce a second signal that is the logical inverse of the first signal. The method then inverts the first signal and inverts the second signal. The method then inverts the first signal and the inverted second signal together and inverts the second signal and the inverted first signal together.

Method and apparatus for level shifting approach with symmetrical resulting waveform

An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Yet another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters, each inverter output is coupled to the next inverter input in the series. The low gain input is coupled to less than all of the inverters within the series.

Method and apparatus for PLL with improved jitter performance

An apparatus is described comprising a noise source coupled to an input of a gain stage. The apparatus also includes a noise shaping stage that forms a shaped noise signal by reducing 1/f noise introduced by the gain stage. The noise shaping stage has an input coupled to an output of the gain stage. The apparatus also has a decision circuit that decides whether the shaped noise signal, or a signal derived from the shaped noise signal corresponds to a 1 or a 0. A method is described that amplifies a first noise signal to produce a second noise signal. A shaped noise signal is formed by reducing 1/f noise introduced to the second noise signal by the amplifying. A random sequence is generated by comparing, against a reference, the shaped noise signal or a signal derived from the shaped noise signal.

Method and apparatus for random sequence generator

A bubble suppression apparatus is disclosed comprising: a first set of AND gates, wherein each AND gate within the first set has an input configured to receive a binary thermometer code value and one or more adjacent binary thermometer code values; and a second set of AND gates, wherein each AND gate within the second set has an input coupled to two or more outputs of the first set of AND gates.

Bubble suppression method and apparatus

An apparatus having a white noise source which is coupled to a gain stage having an amplifier. The gain stage is coupled to a noise shaping stage which is also coupled to a decision circuit. Another apparatus having a white noise source which is differentially coupled to a gain stage that has a cascade of open loop amplifiers. The gain stage is differentially coupled to a noise shaping stage which is also differentially coupled to a decision circuit. A method that involves differentially coupling white noise into a gain stage. The white noise is differentially amplified with an amplifier which produces a first white noise signal. 1/f noise and offset voltage is substantially removed from said first white noise signal to produce a second white noise signal. A random sequence signal is produced by deciding whether the second white noise signal is a 1 or 0.

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Cork, Ireland

John M Horan