United States of America As Represented by the Secretary of the Air Force

Agere Systems Inc.

University of Cincinnati

The University of North Carolina at Charlotte

Other

John M Emmert

Miron Abramovici

James B Y Tsui

Charles Eugene Stroud

David M Lin

Nicholas A Pequignot

Stephen L Hary

Keith M Graves

Waleed Khalil

William S McCormick

Vipul J Patel

John J Schamus

A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.

Efficient Muller C-Element implementation for high bit-width asynchronous applications

Systems and methods of use and fabrication are described for a THx2 threshold gate cell for a programmable gate array including a mode-independent PMOS configuration and an NMOS configuration configured to operate in one of a TH12 mode and a TH22 mode, wherein x is set to a threshold of 1 for the TH12 mode and x is set to a threshold of 2 for the TH22 mode.

Systems and methods for asynchronous programmable gate array devices

In accordance with various embodiments of the disclosed subject matter, a system, apparatus and method is configured to provide a poly-phased, time-interleaved radio frequency (RF) digital-to-analog converter (DAC) suitable for use in radar, radio, mobile and other RF systems.

Poly phased, time-interleaved RF-DAC for multi-function frequency-agile, tunable transmitter

A moderate cost and complexity digital radio receiver system having enhanced instantaneous dynamic range response to the receipt of simultaneous signals and also providing large single signal dynamic range. Multiple signal instantaneous dynamic range improvement is achieved through use of a suppressed zero signal amplitude representation arrangement having a selected number of signal amplitude representing digital bits rather than the larger entire array of digital output bits of the receiver system's analog to digital converter. Digital apparatus for accomplishing the selection of desired high order bits from the analog to digital converter output is also disclosed in detail. Use of a 'Monobit' and related simplified Fourier transformation radio receivers as disclosed in identified previous patents of the recited inventors and colleagues is preferred for embodying the digital radio receiver circuit included in a present system.

Digital receiver instantaneous dynamic range enhancement

A Fourier transformation arrangement usable in an electronic warfare radio receiver for analyzing spectral content of multiple transmitter-sourced brief duration incoming signals for their signal characteristics. The disclosed Fourier transformation arrangement includes approximated Kernel function values disposed in a significant plurality of locations about a real-imaginary coordinate axis origin according to disclosed locating principles. The points are displaced from the origin by magnitudes having real and imaginary component lengths of powers of two commencing with zero. Multiplication involving a power of two component length during a Kernel function utilization are preferably achieved by way of an expanded binary shift multiplication algorithm in lieu of a full fledged digital multiplication algorithm. A group of guiding principles for selecting desirable approximation Kernel function locations is included.

Kernel function approximation and receiver

A method of fault tolerant operation of field programmable gate arrays (FPGAs), whether as an embedded portion of a system-on-chip or other application specific integrated circuit, utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into a self-testing area and a working area. Within the self-testing area, programmable interconnect resources of the FPGA are tested for faults. Upon the detection of one or more faults within the interconnect resources, the faulty interconnect resources are identified and a determination is made whether utilization of the faulty interconnect resources is compatible with an intended operation of the FPGAs. If the faulty interconnect resources are compatible with the intended operation of the FPGA, utilization of the faulty interconnect resource is allowed to provide fault tolerant operation of the FPGA. If the faulty interconnect resources are not compatible with the intended operation of the FPGA, on the other hand, a multi-step reconfiguration process may be initiated which attempts to minimize the effects of each reconfiguration on the overall performance of the FPGA. In an alternate embodiment, the entire FPGA may be configured as one or more self-testing areas during off-line testing, such as manufacturing testing.

Fault tolerant operation of field programmable gate arrays

A method of fault tolerant operation of an adaptive computing system includes identifying a faulty resource in a signal path of the adaptive computing system, reconfiguring the signal path to avoid the faulty resource, estimating a time delay created by reconfiguring the signal path, and adjusting a system clock period to accommodate the time delay. In a preferred embodiment, an FPGA is configured into an initial self-testing area and a working area. Resources located within the self-testing area are tested and faulty resources identified. The FPGA is then reconfigured to avoid the identified faulty resources. When the resources are reconfigured for fault tolerant operation, signal path delays may be introduced into the system. If the signal path delays are in a critical path, a period of a system clock may be adjusted in order to insure proper fault tolerant operation.

Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock

A Fourier transformation system usable for example in an electronic warfare radio receiver for analyzing spectral content of multiple transmitter-sourced brief duration incoming signals for characteristics including frequency component and frequency component amplitude content. The Fourier transformation system includes a plurality of approximated Kernel function values disposed at a plurality of locations about a real-imaginary coordinate axis origin and displaced from the origin by magnitudes having real and imaginary component lengths of unity and powers of two. Multiplication involving a power of two component during a Fourier transformation are achieved in a simple manner commensurate with a multiplication by unity in complexity but involving a binary number shift multiplication operation in lieu of a full fledged digital multiplication. Signal results comparisons with more simplified and more complex Kernel function approximations are also included.

Quadbit kernel function algorithm and receiver

A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously. Prior to relocating the initial self-testing areas, the initial self-testing areas are reconfigured to replace unusable faulty PLBs with spare PLBs. Spare PLBs are initially allocated throughout the working area. Specifically, each operational PLB within the working area is allocated an adjacent preferred spare PLB. Predetermined configurations of the FPGA utilizing the preferred spares are used to avoid the faulty PLBs. If the initially allocated spares are incapable of utilization, then a subsequent portion of the PLBs within the working area are allocated as spares and new replacement configurations determined. As the number of spare PLBs is diminished over time, additional spare PLBs are at some point necessarily removed from the self-testing areas. In this manner, the testing and roving capabilities of the self-testing area are also inevitably diminished. Eventually, roving, testing, and even operation of the FPGA will cease.

Growing community of inventors

Dayton, OH, United States of America

John M Emmert