Nanoamp Solutions, Inc.

Enable Semiconductor, Inc.

Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Virtual Silicon Technology, Inc.

Mosaid Delaware, Inc.

Philips Electronics North America Corporation

Kilopass Technology, Inc.

John M Callahan

Daniel L Hillman

Barry Alan Hoberman

Michael Anthony Zampaglione

Andrew J Cole

William Gordon Walker

Harry Luan

Glen Arnold Rosendale

Hemanshu T Vernenker

Michael David Fliesler

Michael Tooher

Zhongshang Liu

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Low leakage and data retention circuitry

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

3.5 transistor non-volatile memory cell using gate breakdown phenomena

To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals represent addresses of defective memory cells in the ROM. An ADDHIT signal indicates that the ROM has received an address of a defective memory cell. The ADDHIT signal is then timed to provide a REV signal that changes the polarity of the memory bit signal out of a buffer circuit. This corrects an erroneous memory cell by reversing the sense of the memory bit received from a defective memory cell and delivered to an output terminal of the ROM. The REV signal is steered to an output buffer corresponding to the proper ROM chip output pad using a fuse-controlled selection circuit. A plurality of defective memory cells are corrected by using a number of comparators to compare input address signals to a number of fuse-controlled static addresses, each representing a defective memory cell.

ROM error-correction control

A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This consumes less power for a read operation. Senseamps for finally converting low-level signals to full logic output voltage levels are located right next to output buffers and data output pads for the SRAM. The bit lines for a memory CORE are formed in lower metal layers that are closer to the core memory cells and, thus, have higher capacitance. The present invention uses lower-capacitance top layers 4&#x2013;6 of a 6 metal layer scheme for the signal lines of the differential internal data bus. An optimum configuration has the capacitance of a bitline equal to the capacitance of the differential internal data bus bit-line.

SRAM power reduction

A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout and a non-standard, reversed option RO for the layout of the bonding-pads. The double-sized, back-to-back, wire-bonded integrated-circuit chip assembly and method includes a pair of integrated-circuit chips, each having one or more reversible wire-bonding-pads. One of the chips has its wire-bonding-pads electrically reversed such that the wire-bonding pads on both chips are located near each other to accommodate wire-bonding to a common bonding finger of a lead frame. A bonding-option wire-bonding-pad has an external voltage applied to it to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or a reversed pattern for the reversible wire-bonding-pads. A voltage sensor circuit senses the voltage applied to the bonding-option wire-bonding-pad and alternatively generates either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.

Dual die memory

A fuse-controlled, row-redundancy control system and method for a SRAM includes a multi-bit, defective-row storage array of static circuits that are programmed to store one of the address bits of a predetermined defective row of the SRAM and that includes a single fuse. The single fuse is blown to indicate a first state of the one of the address bits and is not blown to indicate a second state of the one address bit. The address bits of the predetermined defective row of the SRAM are compared with corresponding address bits of row-address signals received by the SRAM. The comparator includes a fuseless, exclusive logic circuit and provides a RFLAG control signal that indicates that the stored address bits of the defective row of the SRAM match the respective received row address bits for the SRAM. The RFLAG control signal disables a word line corresponding to the defective row of the SRAM and also enables a redundant SRAM word line corresponding to a redundant SRAM row so that a redundant SRAM row is substituted for the defective row of the SRAM.

SRAM row redundancy

To alleviate the crosstalk between BL and BLN of the same column, the present invention provides vertical twisting for the bit line and the complementary bit line of a line pair connecting a column of memory bits to a sense amplifier. The BL and BLN run in the same direction, but never within same metal layer and never overlying each other. To provide vertical twisting, horizontal and vertical switching are done in the same crossover channels so that BL and BLN have the same length in order to keep the overall capacitance of each line the same. Triple standard twist regions can be used for both the horizontal and vertical twists. The capacitance between BL and BLN are substantially reduced as well as the capacitance to neighboring column BLs and BLNs. Capacitive coupling between a BL and a BLN of the same column is reduced to thereby prevent reduction of the voltage difference, or delta voltage, presented to the differential input terminals of a senseamp.

Growing community of inventors

San Ramon, CA, United States of America

John M Callahan