International Business Machines Corporation

John M Blondin

Eric Gerhard Liniger

Donald W Brouillette

Robert F Cook

Ronald Lee Mendelson

Gene T Patrick

David Frederick Diefenderfer

Woody Ray Smith

David J Rich

Jeffrey Jay Jones

Kevin M Potasiewicz

An apparatus and a method for testing semiconductor devices such as integrated circuits having a handler for picking up an integrated circuit to be tested and placing the picked up integrated circuit into an automatic circuit test apparatus. When the circuit to be tested is inserted into the test apparatus an extraneous signal shield is automatically engaged to enclose the device being tested and protect the circuit, being tested, from stray extraneous electromagnetic signals during the test thereby preventing said stray electromagnetic interference from inducing errors in the tested circuit.

Apparatus for preventing cross talk and interference in semiconductor devices during test

A semi-conductor module burn-in test apparatus having a plurality burn-in boards each of which is provided a plurality of module test sockets thereon and each test socket is coupled to an adjacent test socket by with a high current, open/short split power connector that can readily connected to or disconnected from said adjacent test socket by coupling together the power inputs of the adjacent sockets or uncoupling the previously coupled power inputs of adjacent sockets and thereby selectively altering the current carrying levels available to said adjacent test sockets.

Semiconductor test and burn-in apparatus provided with a high current power connector for combining power planes

A container system for storing and transporting sensitive components such as semiconductor chips is disclosed. The container system includes in combination, a housing and a plurality of component carriers for receiving components to be stored and transported in stacked banks. The plurality of component carriers are stacked one on top of the other in a top-to-bottom stacked arrangement within the housing. An underside bottom surface of a first component carrier provides a top cover to a second component carrier positioned immediately below the first component carrier, wherein a component carrier includes a compartmental core for storing components on a top surface thereof in segmented row compartments, each segmented row compartment having sidewall surfaces and a bottom surface. The component carrier further includes an underside surface characterized by unidirectional waves having a prescribed wave amplitude and a prescribed wave period, the wave amplitude and wave period selected for simultaneously providing a reduced surface tension to a top surface of a component part and a reduced potential for damage to protruding surface features on a top surface of the component part, respectively, the component part further for being stored in a row compartment of an underlying component carrier in the stacked arrangement.

Component carrier having a wave pattern tension reduction surface

A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information

Method and apparatus for preventing chip breakage during semiconductor

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Colchester, VT, United States of America

John M Blondin